View MAX17480_5572843.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX17480 is a triple-output, step-down, fixed- frequency controller for amds serial vid interface (svi) cpu and northbridge (nb) core supplies. the MAX17480 consists of two high-current smpss for the cpu cores and one 4a internal switch smps for the nb core. the two cpu core smpss run 180 out-of-phase for true interleaved operation, minimizing input capacitance. the 4a internal switch smps runs at twice the switching frequency of the core smps, reducing the size of the external components. the MAX17480 is fully amd svi compliant. output volt- ages are dynamically changed through a 2-wire svi, allowing the smpss to be individually programmed to different voltages. a slew-rate controller allows con- trolled transitions between vid codes and controlled soft-start. svi also allows each smps to be individually set into a low-power pulse-skipping state. transient phase repeat improves the response of the fixed-frequency architecture, reducing the total output capacitance for the cpu core. a thermistor-based tem- perature sensor provides a programmable thermal-fault output ( vrhot ). the MAX17480 includes output overvoltage protection (ovp), undervoltage protection (uvp), and thermal pro- tection. when any of these protection features detect a fault, the controller shuts down. true differential current sensing improves current limit and load-line accuracy. the MAX17480 has an adjustable switching frequency, allowing 100khz to 600khz operation per core smps, and twice that for the nb smps. applications mobile amd svi core supplies multiphase cpu core supplies voltage-positioned, step-down converters notebook/desktop computers features dual-output fixed-frequency core supply controller split or combinable outputs detected at power-up dynamic phase selection optimizes active/sleep efficiency transient phase repeat reduces output capacitance true out-of-phase operation reduces input capacitance programmable ac and dc droop accurate current balance and current limit integrated drivers for large synchronous- rectifier mosfets programmable 100khz to 600khz switching frequency 4v to 26v battery input voltage range 4a internal switch northbridge smps 2.7v to 5.5v input voltage range 2x programmable switching frequency 75m ? /40m ? power switches ?.5% v out accuracy over line, load, and temperature amd svi-compliant serial interface with switchable address 7-bit on-board dac: 0 to +1.550v output adjust range integrated boost switches adjustable slew-rate control power-good (pwrgd) and thermal-fault ( vrhot ) outputs system power-ok (pgd_in) input overvoltage, undervoltage, and thermal-fault protection voltage soft-startup and passive shutdown < 1? typical shutdown current MAX17480 amd 2-/3-output mobile serial vid controller ________________________________________________________________ maxim integrated products 1 ordering information 19-4443; rev 0; 2/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX17480gtl+ -40 c to +105 c 40 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. pin configuration appears at end of data sheet.
MAX17480 amd 2-/3-output mobile serial vid controller 2 _______________________________________________________________________________________ absolute maximum ratings (note 1) electrical characteristics (circuit of figure 2, v in = 12v, v cc = v dd = v in3 = shdn = pgd_in = 5v, v ddio = 1.8v, option = gnds_ = agnd = pgnd, fbdc_ = fbac_ = out3 = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd, v in3, v cc , v ddio to agnd ..............................-0.3v to +6v pwrgd to agnd .....................................................-0.3v to +6v shdn to agnd ........................................................-0.3v to +6v gnds1, gnds2, thrm, vrhot to agnd..............-0.3v to +6v csp_, csn_, ilim12 to agnd .................................-0.3v to +6v svc, svd, pgd_in to agnd ...................................-0.3v to +6v fbdc_, fbac_, out3 to agnd ..............................-0.3v to +6v osc, time, option, ilim3 to agnd ........-0.3v to (v cc + 0.3v) bst1, bst2 to agnd .............................................-0.3v to +36v bst1, bst2 to v dd .................................................-0.3v to +30v bst3 to agnd...................................(v dd - 0.3v) to (v lx3 + 6v) lx1 to bst1..............................................................-6v to +0.3v lx3 rms current (note 2) .....................................................4a lx2 to bst2..............................................................-6v to +0.3v lx3 to pgnd (note 2) ..............................................-0.6v to +6v dh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) dh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) dl1 to pgnd ..............................................-0.3v to (v dd + 0.3v) dl2 to pgnd ..............................................-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70 c) 40-pin tqfn (derate 22.2mw/ c above +70 c) .......1778mw operating temperature range .........................-40 c to +105 c junction temperature ......................................................+150 c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units input supplies v in drain of external high-side mosfet 4 26 v bias v cc , v dd 4.5 5.5 v in3 2.7 5.5 input voltage range v ddio 1.0 2.7 v v cc undervoltage-lockout threshold v uvlo v cc rising, 50mv typical hysteresis, latched, uv fault 4.10 4.25 4.45 v v cc power-on reset threshold falling edge, typical hysteresis = 1.1v, faults cleared and dl_ forced high when v cc falls below this level 1.8 v v ddio undervoltage-lockout threshold v ddio rising, 100mv typical hysteresis, latched, uv fault 0.7 0.8 0.9 v v in3 undervoltage-lockout threshold v in3 rising, 100mv typical hysteresis 2.5 2.6 2.7 v quiescent supply current (v cc ) i cc skip mode, fbdc_ and out3 forced above their regulation points 5 10 ma quiescent supply currents (v dd ) i dd skip mode, fbdc_ and out3 forced above their regulation points, t a = +25c 0.01 1 a quiescent supply current (v ddio ) i ddio 10 25 a quiescent supply current (in3) i in3 skip mode, out3 forced above its regulation point 50 200 a shutdown supply current (v cc ) shdn = gnd, t a = +25c 0.01 1 a note 1: absolute maximum ratings measured with 20mhz scope bandwidth. note 2: lx3 has clamp diodes to pgnd and in3. if continuous current is applied through these diodes, thermal limits must be observed.
MAX17480 amd 2-/3-output mobile serial vid controller _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units shutdown supply currents (v dd ) shdn = gnd, t a = +25c 0.01 1 a shutdown supply current (v ddio ) shdn = gnd, t a = +25c 0.01 1 a shutdown supply current (in3) shdn = gnd, t a = +25c 0.01 1 a internal dacs, slew rate, phase shift dac codes from 0.8375v to 1.5500v -0.5 +0.5 % dac codes from 0.5000v to 0.8250v -5 +5 dc output voltage accuracy (note 1) v out measured at fbdc_ for the core smpss; measured at out3 for the nb smps; 30% duty cycle, no load, ilim3 = v cc , v out3 = v dac3 + 12.5mv (note 3) dac codes from 12.5mv to 0.4875v -10 +10 mv out3 offset 12.5 mv 50 % smps1 to smps2 phase shift smps2 starts after smps1 180 degrees smps3 to smps1 and smps2 phase shift smps3 starts after smps1 or smps2 25 % r time = 143k , sr = 6.25mv/s -10 +10 during transition r time = 35.7k to 357k , sr = 25mv/s to 2.5mv/s -15 +15 % slew-rate accuracy startup 1 mv/s fbac_ input bias current i fbac _csp_ = csn_, t a = +25c -3 +3 a fbdc_ input bias current i fbdc _t a = +25c -250 +250 na r osc = 143k (f osc1 = f osc2 = 300khz nominal, f osc3 = 600khz nominal) -7 +7 switching frequency accuracy f osc1, f osc2, f osc3 r osc = 71.4k (f osc1 = f osc2 = 600khz nominal, f osc3 = 1.2mhz nominal) to 432k (f osc1 = f osc2 = 99khz nominal, f osc3 = 199khz nominal) -9 +9 % smps1 and smps2 controllers dc load regulation either smps, pwm mode, droop disabled; zero to full load -0.1 % line regulation error either smps, 4v < v in < 26v 0.03 %/v gnds_ input range v gnds_ separate mode -200 +200 mv gnds_ gain a gnds_ separate: v out _/ v gnds _ , -200mv v gnds _ +200mv; combined: v out / v gnds_, -200mv v gnds_ +200mv 0.95 1.00 1.05 v/v gnds_ input bias current i gnds _t a = +25c -2 +2 a electrical characteristics (continued) (circuit of figure 2, v in = 12v, v cc = v dd = v in3 = shdn = pgd_in = 5v, v ddio = 1.8v, option = gnds_ = agnd = pgnd, fbdc_ = fbac_ = out3 = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.)
MAX17480 amd 2-/3-output mobile serial vid controller 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 2, v in = 12v, v cc = v dd = v in3 = shdn = pgd_in = 5v, v ddio = 1.8v, option = gnds_ = agnd = pgnd, fbdc_ = fbac_ = out3 = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units combined-mode detection threshold gnds1, gnds2, detection after refok, latched, cleared by cycling shdn 0.7 0.8 0.9 v maximum duty factor d max 90 92 % minimum on-time t onmin 150 ns smps1 and smps2 current limit current-limit threshold tolerance v limit v csp _ - v csn _ = 0.052 x (v ref - v ilim ), (v ref - v ilm ) = 0.2v to 1.0v -3 +3 mv zero-crossing threshold v zx v gnd _ - v lx _, skip mode 1 mv idle mode? threshold v imin v csp _ - v csn _, skip mode, 0.15 x v limit -2 +2 mv cs_ input leakage current csp_ and csn_, t a = +25c -0.2 +0.2 a cs_ common-mode input range csp_ and csn_ 0 2 v smps1 and smps2 droop, current balance, and transient response ac droop and current balance amplifier transconductance g m(fbac _ ) i fbac _/( v cs _), v fbac _ = v csn _ = 1.2v, v csp _ - v csn _ = 0 to +40mv 1.94 2.00 2.06 ms ac droop and current balance amplifier offset i fbac _/g m(fbac _ ) -1.5 +1.5 mv no-load positive offset option = 2v or gnd +12.5 mv transient detection threshold measured at fbdc_ with respect to steady-state fbdc_ regulation voltage, 10mv hysteresis (typ) -47 -41 -33 mv smps3 internal 4a step-down converter out3 load regulation r droop3 4 5.5 7 mv/a out3 line regulation 0 to 100% duty cycle 5 mv out3 input current i out3 t a = +25c -100 -5 +100 na lx3 leakage current i lx3 shdn = gnd, v lx3 = gnd or 5.5v, v in3 = 5.5v, t a = +25c -20 +20 a r on(nh3) high-side n-channel 75 150 internal mosfet on-resistance r on(nl3) low-side n-channel 40 75 m ilim3 = v cc 4.75 5.25 6 lx3 peak current limit i lx3pk ilim3 = gnd 3.75 4.25 5 a lx3 idle-mode trip level i lx3min percentage of i lx3pk 25 % lx3 zero-crossing trip level i zx3 skip mode 20 ma maximum duty factor d max 84 87 % minimum on-time t onmin 150 ns idle mode is a trademark of maxim integrated products, inc.
MAX17480 amd 2-/3-output mobile serial vid controller _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 2, v in = 12v, v cc = v dd = v in3 = shdn = pgd_in = 5v, v ddio = 1.8v, option = gnds_ = agnd = pgnd, fbdc_ = fbac_ = out3 = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units fault detection pwm mode 250 300 350 mv skip mode and output has not reached the regulation voltage 1.80 1.85 1.90 output overvoltage trip threshold (smps1 and smps2 only) v ovp_ measured at fbdc_, rising edge minimum ovp threshold 0.8 v output overvoltage fault propagation delay (smps1 and smps2 only) t ovp fbdc_ forced 25mv above trip threshold 10 s output undervoltage protection trip threshold v uvp measured at fbdc_ or out3 with respect to unloaded output voltage -450 -400 -350 mv output undervoltage fault propagation dela y t uvp fbdc_ forced 25mv below trip threshold 10 s lower threshold, falling edge (undervoltage) -350 -300 -250 pwrgd threshold measured at fbdc_ or out3 with respect to unloaded output voltage,15mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +200 +250 mv pwrgd propagation delay t pwrgd fbdc_ or out3 forced 25mv outside the pwrgd trip thresholds 10 s pwrgd, output low voltage i sink = 4ma 0.4 v pwrgd leakage current i pwrgd high state, pwrgd forced to 5.5v, t a = +25c 1 a pwrgd startup delay and transition blanking time t blank measured from the time when fbdc_ and out3 reach the target voltage 20 s vrhot trip threshold measured at thrm, with respect to v cc , falling edge, 115mv hysteresis (typ) 29.5 30 30.5 % vrhot delay t vrhot thrm forced 25mv below the vrhot trip threshold, falling edge 10 s vrhot , output low voltage i sink = 4ma 0.4 v vrhot leakage current high state, vrhot forced to 5v, t a = +25c 1 a thrm input leakage t a = +25c -100 +100 na thermal-shutdown threshold t shdn hysteresis = 15c +160 c gate drivers high state (pullup) 0.9 2.5 dh_ gate-driver on-resistance r on(dh _ ) bst_ - lx_ forced to 5v (note 4) low state (pulldown) 0.7 2.5 dl_, high state 0.7 2.0 dl_ gate-driver on-resistance r on(dl _ ) dl_, low state 0.25 0.6
MAX17480 amd 2-/3-output mobile serial vid controller 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 2, v in = 12v, v cc = v dd = v in3 = shdn = pgd_in = 5v, v ddio = 1.8v, option = gnds_ = agnd = pgnd, fbdc_ = fbac_ = out3 = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units dh_ gate-driver source/sink current i dh _ dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2.2 a dl_ gate-driver source current i dl _ dl_ forced to 2.5v 2.7 a dl_ gate-driver sink current i dl _ (sink) dl_ forced to 2.5v 8 a t dh _ dl dh_ low to dl_ high 9 20 35 dead time t dl _ dh dl_ low to dh_ high 9 20 35 ns internal bst1, bst2 switch r on bst1, bst2 to v dd , i bst1 = i bst2 = 10ma 10 20 internal bst3 switch r on bst3 to v dd , i bst3 = 10ma 10 20 2-wire i 2 c bus logic interface svi logic-input current svc, svd, t a = +25c -1 +1 a svi logic-input threshold svc, svd, rising edge, hysteresis 0.14 x v ddio (v) 0.3 x v ddio 0.7 x v ddio v svc clock frequency f svc 3.4 mhz start condition hold time t hd;sta 160 ns repeated start condition setup time t su;sta 160 ns stop condition setup time t su;sto 160 ns data hold t hd;dat a master device must internally provide a hold time of at least 300ns for the svd signal (referred to the v ihmin of svc signal) to bridge the undefined region of svcs falling edge 70 ns data setup time t su;dat 10 ns svc low period t low 160 ns svc high period t high measured from 10% to 90% of v ddio 60 ns svc/svd rise and fall time t r , t f input filters on svd and svc suppress noise spike less than 50ns 40 ns pulse width of spike suppression 20 ns inputs and outputs shdn , pgd_in, t a = +25c -1 +1 a logic-input current ilim3, option, t a = +25c -200 +200 na logic-input levels shdn , rising edge, hysteresis = 225mv 0.8 2.0 v high, option, ilim3 v cc - 0.4 3.3v, option 2.75 3.85 2v, option 1.65 2.35 input logic levels low, option, ilim3 0.4 v pgd_in logic-input threshold pgd_in, rising edge, hysteresis = 65mv 0.3 x v ddio 0.7 x v ddio v
MAX17480 amd 2-/3-output mobile serial vid controller _______________________________________________________________________________________ 7 electrical characteristics (circuit of figure 2, v in = 12v, v cc = v dd = v in3 = shdn = pgd_in = 5v, v ddio = 1.8v, option = gnds_ = agnd = pgnd, fbdc_ = fbac_ = out3 = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = -40? to +105? , unless otherwise noted. typical values are at t a = +25 c.) (note 5) parameter symbol conditions min typ max units input supplies v in drain of external high-side mosfet 4 26 v bias v cc , v dd 4.5 5.5 v in3 2.7 5.5 input voltage range v ddio 1.0 2.7 v v cc undervoltage-lockout threshold v uvlo v cc rising, 50mv typical hysteresis, latched, uv fault 4.10 4.45 v v ddio undervoltage-lockout threshold v ddio rising, 100mv typical hysteresis, latched, uv fault 0.7 0.9 v v in3 undervoltage-lockout threshold v in3 rising, 100mv typical hysteresis 2.5 2.7 v quiescent supply current (v cc ) i cc skip mode, fbdc_ and out3 forced above their regulation points 10 ma quiescent supply current i ddio 25 a quiescent supply current (in3) i in3 skip mode, out3 forced above its regulation point 200 a internal dacs, slew rate, phase shift dac codes from 0.8375v to 1.5500v -0.7 +0.7 % dac codes from 0.5000v to 0.8250v -7.5 +7.5 dc output voltage accuracy v out measured at fbdc_ for the core smpss; measured at out3 for the nb smps; 30% duty cycle, no load, ilim3 = v cc , v out3 = v dac3 + 12.5mv (note 3) dac codes from 12.5mv to 0.4875v -15 +15 mv r time = 143k , sr = 6.25mv/s -10 +10 slew-rate accuracy during transition r time = 35.7k to 357k , sr = 25mv/s to 2.5mv/s -15 +15 % r osc = 143k (f osc1 = f osc2 = 300khz nominal, f osc3 = 600khz nominal) -9 +9 switching frequency accuracy f osc1, f osc2, f osc3 r osc = 71.4k (f osc1 = f osc2 = 600khz nominal, f osc3 = 1.2mhz nominal) to 432k (f osc1 = f osc2 = 99khz nominal, f osc3 = 199khz nominal) -12 +12 %
MAX17480 amd 2-/3-output mobile serial vid controller 8 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 2, v in = 12v, v cc = v dd = v in3 = shdn = pgd_in = 5v, v ddio = 1.8v, option = gnds_ = agnd = pgnd, fbdc_ = fbac_ = out3 = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = -40? to +105? , unless otherwise noted. typical values are at t a = +25 c.) (note 5) parameter symbol conditions min typ max units smps1 and smps2 controllers gnds_ input range v gnds_ separate mode -200 +200 mv gnds_ gain a gnds_ separate: v out _/ v gnds _ , -200mv v gnds _ +200mv ; combined; v out / v gnds_, -200mv v gnds_ +200mv 0.95 1.05 v/v combined-mode detection threshold gnds1, gnds2, detection after refok, latched, cleared by cycling shdn 0.7 0.9 v maximum duty factor d max 90 % minimum on-time t onmin 150 ns smps1 and smps2 current limit current-limit threshold tolerance v limit v csp _ - v csn _ = 0.052 x (v ref - v ilim ), (v ref - v ilm ) = 0.2v to 1.0v -3 +3 mv idle-mode threshold tolerance v imin v csp _ - v csn _, skip mode, 0.15 x v limit -2 +2 mv cs_ common-mode input range csp_ and csn_ 0 2 v smps1 and smps2 droop, current balance, and transient response ac droop and current balance amplifier transconductance g m(fbac _ ) i fbac _/( v cs _), v fbac _ = v csn _ = 1.2v, v csp _ - v csn _ = 0 to +40mv 1.94 2.06 ms ac droop and current balance amplifier offset i fbac _/g m(fbac _ ) -1.5 +2.0 mv transient detection threshold measured at fbdc_ with respect to steady-state fbdc_ regulation voltage, 10mv hysteresis (typ) -47 -33 mv smps3 internal 4a step-down converter out3 load regulation r droop3 4 7 mv/a r on(nh3) high-side n-channel 150 internal mosfet on-resistance r on(nl3) low-side n-channel 75 m lx3 peak current limit i lx3pk ilim3 = v cc, skip mode 4.75 6 a maximum duty factor d max 84 % minimum on-time t onmin 150 ns
MAX17480 amd 2-/3-output mobile serial vid controller _______________________________________________________________________________________ 9 electrical characteristics (continued) (circuit of figure 2, v in = 12v, v cc = v dd = v in3 = shdn = pgd_in = 5v, v ddio = 1.8v, option = gnds_ = agnd = pgnd, fbdc_ = fbac_ = out3 = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = -40? to +105? , unless otherwise noted. typical values are at t a = +25 c.) (note 5) parameter symbol conditions min typ max units fault detection pwm mode 250 350 mv output overvoltage trip threshold (smps1 and smps2 only) v ovp_ measured at fbdc_, rising edge skip mode and output have not reached the regulation voltage 1.80 1.90 v output undervoltage protection trip threshold v uvp measured at fbdc_ or out3 with respect to unloaded output voltage -450 -350 mv lower threshold, falling edge (undervoltage) -350 -250 pwrgd threshold measured at fbdc_ or out3 with respect to unloaded output voltage, 15mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +250 mv pwrgd, output low voltage i sink = 4ma 0.4 v vrhot trip threshold measured at thrm, with respect to v cc, falling edge, 115mv hysteresis (typ) 29.5 30.5 % vrhot , output low voltage i sink = 4ma 0.4 v gate drivers high state (pullup) 2.5 dh_ gate-driver on-resistance r on(dh _ ) bst_ - lx_ forced to 5v (note 4) low state (pulldown) 2.5 dl_, high state 2.0 dl_ gate-driver on-resistance r on(dl _ ) dl_, low state 0.6 t dh _ dl dh_ low to dl_ high 9 35 dead time t dl _ dh dl_ low to dh_ high 9 35 ns internal bst1, bst2 switch r on bst1, bst2 to v dd , i bst1 = i bst2 = 10ma 20 internal bst3 switch r on bst3 to v dd , i bst3 = 10ma 20 2-wire i 2 c bus logic interface svi logic-input threshold svc, svd, rising edge, hysteresis = 0.14 x v ddio (v) 0.3 x v ddio 0.7 x v ddio v svc clock frequency f svc 3.4 mhz start condition hold time t su;sta 160 ns repeated start condition setup time t su;sta 160 ns stop condition setup time t su;sto 160 ns data hold t hd;dat a master device must internally provide a hold time of at least 300ns for the svd signal (referred to the v ihmin of svc signal) to bridge the undefined region of svcs falling edge 70 ns
MAX17480 amd 2-/3-output mobile serial vid controller 10 ______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 2, v in = 12v, v cc = v dd = v in3 = shdn = pgd_in = 5v, v ddio = 1.8v, option = gnds_ = agnd = pgnd, fbdc_ = fbac_ = out3 = csp_ = csn_ = 1.2v, all dac codes set to the 1.2v code, t a = -40? to +105? , unless otherwise noted. typical values are at t a = +25 c.) (note 5) parameter symbol conditions min typ max units data setup time t su;dat 10 ns svc low period t low 160 ns svc high period t high measured from 10% to 90% of v ddio 60 ns svc/svd rise and fall time t r , t f input filters on svd and svc suppress noise spike less than 50ns 40 ns inputs and outputs logic-input levels shdn , rising edge, hysteresis = 225mv 0.8 2.0 v high, option, ilim3 v cc - 0.4 3.3v, option 2.75 3.85 2v, option 1.65 2.35 input logic levels low, option, ilim3 0.4 v pgd_in logic-input threshold pgd_in, rising edge, hysteresis = 65mv 0.3 x v ddio 0.7 x v ddio v note 3: when the inductor is in continuous conduction, the output voltage has a dc regulation level lower than the error-comparator threshold by 50% of the ripple. in discontinuous conduction, the output voltage has a dc regulation level higher than the error-comparator threshold by 50% of the ripple. the core smpss have an integrator that corrects for this error. the nb smps has an offset determined by the ilim3 pin, and a -6.5mv/a load line. note 4: production testing limitations due to package handling require relaxed maximum on-resistance specifications for the tqfn package. note 5: specifications to t a = -40 c to +105 c are guaranteed by design, not production tested. svc t hd;sta t hd;dat t su;dat t su;sto t buf t low t high t r t f v ih v il svd figure 1. timing definitions used in the electrical characteristics
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 11 typical operating characteristics ( circuit of figure 2, v in = 12v, v dd = v cc = 5v, v ddio = 2.5v, t a = +25 c, unless otherwise noted .) core smps 1-phase efficiency vs. load current (v out = 1.2v) MAX17480 toc01 load current (a) efficiency (%) 10 1 70 80 90 100 60 0.1 100 skip mode pwm mode 12v 7v 20v core smps 2-phase efficiency vs. load current (v out = 1.2v) MAX17480 toc02 load current (a) efficiency (%) 10 70 80 90 100 60 1100 12v 7v 20v pwm mode core smps output voltage vs. load current (v out = 1.2v) MAX17480 toc03 load current (a) output voltage (v) 15 10 5 1.195 1.200 1.205 1.190 020 skip mode and pwm mode v in = 12v core smps 1-phase efficiency vs. load current (v out = 0.8v) MAX17480 toc04 load current (a) efficiency (%) 10 1 70 80 90 100 60 0.1 100 skip mode pwm mode 12v 7v 20v core smps output voltage vs. load current (v out = 0.8v) MAX17480 toc05 load current (a) output voltage (v) 15 10 5 0.795 0.800 0.805 0.790 020 skip mode and pwm mode v in = 12v nb smps efficiency vs. load current (1v) MAX17480 toc06 load current (a) efficiency (%) 1 70 80 90 100 60 0.1 10 skip mode pwm mode 3.3v 5v nb smps 1v output voltage vs. load current MAX17480 toc07 load current (a) output voltage (v) 2 1 0.97 0.99 1.01 1.03 1.05 0.95 04 3 skip mode pwm mode v in = 3.3v v in = 5v core smps 1-phase switching frequency vs. load current MAX17480 toc08 load current (a) switching frequency (khz) 10 1 150 200 250 300 350 100 0.1 100 v in = 20v skip v in = 20v pwm v in = 12v skip v in = 12v pwm v in = 7v skip v in = 7v pwm v out = 1.2v nb smps switching frequency vs. load current MAX17480 toc09 load current (a) switching frequency (khz) 3.0 3.5 2.5 2.0 0.5 1.0 1.5 450 500 550 600 650 700 750 400 04.0 v in = 3.3v skip v in = 5v pwm v in = 3.3v skip v in = 5v pwm v out = 1v
MAX17480 amd 2-/3-output mobile serial vid controller 12 ______________________________________________________________________________________ typical operating characteristics (continued) ( circuit of figure 2, v in = 12v, v dd = v cc = 5v, v ddio = 2.5v, t a = +25 c, unless otherwise noted .) maximum inductor current vs. input voltage MAX17480 toc10 input voltage (v) inductor current (a) 20.0 17.5 12.5 15.0 10.0 7.5 23 25 27 29 31 21 5.0 v out = 1.2v peak current dc current no-load supply current vs. input voltage MAX17480 toc11 input voltage (v) supply current (ma) 24 21 18 15 12 9 6 0.1 1 10 100 0.01 3 skip mode pwm mode i in i in i cc + i dd i cc + i dd v out = 1.2v core smps vid = 1.2v output voltage distribution MAX17480 toc12 output voltage (v) sample percentage (%) 10 20 30 40 50 60 90 80 70 0 1.195 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 1.205 t a = +85 c t a = +25 c sample size = 100 nb smps vid = 1.2v output voltage distribution MAX17480 toc13 output voltage (v) sample percentage (%) 10 20 30 40 50 70 60 0 1.195 1.196 1.197 1.198 1.199 1.200 1.201 1.202 1.203 1.204 1.205 sample size = 100 t a = +85 c t a = +25 c g m(fbac) transconductance distribution MAX17480 toc14 transconductance ( s) sample percentage (%) 5 10 15 20 25 30 0 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012 2015 sample size = 100 +85 c +25 c nb smps peak current-limit distribution MAX17480 toc15 peak current limit (a) sample percentage (%) 5 15 10 20 25 30 0 5.00 5.05 5.10 5.15 5.20 5.25 5.30 5.40 5.35 5.45 5.50 sample size = 100 ilim3 = v cc t a = +85 c t a = +25 c
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 13 typical operating characteristics (continued) ( circuit of figure 2, v in = 12v, v dd = v cc = 5v, v ddio = 2.5v, t a = +25 c, unless otherwise noted .) startup waveforms MAX17480 toc16 200 s/div 0 shdn, 5v/div v out1 , 0.5v/div v out2 , 0.5v/div v out3 , 0.5v/div pwrgd, 5v/div i lx , 5a/div i lx3 , 1a/div v in = 12v v boot = 1v i load1 = 3a i load2 = 3a i load3 = 0.5a 0 0 0 0 5a 0 1a 0 startup sequence MAX17480 toc17 400 s/div 0 shdn, 5v/div v out1 , 0.5v/div v out2 , 0.5v/div v out3 , 0.5v/div pwrgd, 5v/div pgd_in, 2.5v/div svc, 2.5v/div svd, 2.5v/div v in = 12v v boot = 1v v svid = 1.2v 0 0 0 0 0 0 0 shutdown waveforms MAX17480 toc18 100 s/div 3.3v 1.2v 1.2v 1.2v 5v 5v 5v 5v shdn, 5v/div v out1 , 0.5v/div v out2 , 0.5v/div v out3 , 0.5v/div dl1, 10v/div dl2, 10v/div lx3, 10v/div pwrgd, 10v/div v in = 12v i load1 = 3a v svid = 1.2v i load2 = 3a i load3 = 0.5a core smps 1-phase load-transient response MAX17480 toc19 20 s/div 1.2v 1.5a 13.5a 12v 0 v out1 , 50mv/div i lx1 , 10a/div lx1, 10v/div v in = 12v i load1 = 1.5a to 13.5a to 1.5a v out1 = 1.2v pwm mode
core smps 1-phase transient phase repeat MAX17480 toc20 2 s/div 1.2v 1.5a 13.5a 12v 0 v out1 50mv/div i lx1 10a/div lx1 10v/div v in = 12v i load1 = 1.5a to 13.5a to 1.5a v out1 = 1.2v pwm mode core smps 2-phase load-transient response MAX17480 toc21 20 s/div 1.2v 1.5a 13.5a 13.5v 1.5a v out 50mv/div i lx1 10a/div i lx2 10a/div v in = 12v i load = 3a to 27a to 3a v out1 = 1.2v pwm mode core smps 2-phase transient phase repeat MAX17480 toc22 2 s/div 1.2v 1.5a 13.5a 13.5a 1.5a v out 50mv/div i lx1 10a/div i lx2 10a/div v in = 12v i load = 3a to 27a to 3a v out1 = 1.2v pwm mode nb smps load-transient response MAX17480 toc23 20 s/div 1v 0.4a 3.6a 5v 0 v out3 50mv/div i lx3 2a/div lx3 5v/div v in3 = 5v i load3 = 0.4a to 3.6a to 0.4a v out3 = 1v pwm mode MAX17480 amd 2-/3-output mobile serial vid controller 14 ______________________________________________________________________________________ typical operating characteristics (continued) ( circuit of figure 2, v in = 12v, v dd = v cc = 5v, v ddio = 2.5v, t a = +25 c, unless otherwise noted .)
typical operating characteristics (continued) ( circuit of figure 2, v in = 12v, v dd = v cc = 5v, v ddio = 2.5v, t a = +25 c, unless otherwise noted .) core smps output overload waveform (separate mode) MAX17480 toc24 100 s/div 1.2v 1.2v 1.2v 5v 5v 5v 5v 0 0 0 v in = 12v i load1 = 3a to 40a v svid = 1.2v i load2 = 3a i load3 = 0.5a shdn, 5v/div v out1 , 1v/div dl1, 10v/div v out2 , 1v/div v out3 , 1v/div dl2, 10v/div lx3, 10v/div core smps output overvoltage waveform (separate mode) MAX17480 toc25 100 s/div 1.2v 1.2v 1.2v 5v 5v 5v 0 0 0 v in = 12v i load1 = no load v svid = 1.2v i load2 = 3a i load3 = 0.5a shdn, 5v/div v out1 , 1v/div dl1, 10v/div v out2 , 1v/div v out3 , 1v/div dl2, 10v/div lx3, 10v/div dynamic output-voltage transitions (light load) MAX17480 toc26 100 s/div 0.6v 0.6v 0.6v 1.3v 1.3v 2.5v 2.5v 1.3v v in = 12v v svid = 1.3v to 0.6v to 1.3v v out1 , 0.5v/div v out2 , 0.5v/div v out3 , 0.5v/div svc, 2.5v/div svd, 2.5v/div pgd_in transition (light load) MAX17480 toc27 10 s/div 0.8v 0 0 1.1v 1.1v 1.2v 5v 5v 0 0 0 0.9v v in = 12v v boot = 1.1v v out1 = 0.8v v out2 = 1.2v v out3 = 0.9v v out , 200mv/div, v out2 , 200mv/div lx1, 20v/div lx2, 20v/div lx3, 5v/div v out3 , 200mv/div pwrgd, 5v/div pgd_in, 5v/div MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 15
MAX17480 amd 2-/3-output mobile serial vid controller 16 ______________________________________________________________________________________ pin description pin name function 1 ilim12 smps1 and smps2 current-limit adjust input. the positive current-limit threshold voltage is 0.052 times the voltage between time and ilim over a 0.2v to 1.0v range of v(time, ilim). the i min12 minimum current-limit threshold voltage in skip mode is precisely 15% of the corresponding positive current-limit threshold voltage. 2 ilim3 smps3 current-limit adjust input. two-level current-limit setting for smps3. the i lx3min minimum current-limit threshold in skip mode is precisely 25% of the corresponding positive current-limit threshold. ilim3 i lx3pk (a) v cc 5.25 gnd 4.25 3, 4 in3 internal high-side mosfet drain connection for smps3. bypass to pgnd with a 10f or greater ceramic capacitor close to the ic. 5, 6 lx3 inductor connection for smps3. connect lx3 to the switched side of the inductor. 7 bst3 boost flying capacitor connection for smps3. an internal switch between v dd and bst3 charges the flying capacitor during the time the low-side fet is on. 8 shdn active-low shutdown control input. this input cannot withstand the battery voltage. connect to v cc for normal operation. connect to ground to put the ic into its 1a max shutdown state. during startup, the output voltage is ramped up to the voltage set by the svc and svd inputs at a slew rate of 1mv/s. in shutdown, the outputs are discharged using a 20 switch through the csn_ pins for the core smpss and through the out3 pin for the northbridge smps. the MAX17480 powers up to the voltage set by the two svi bits. svc svd boot voltage v out (v) 0 0 1.1 0 1 1.0 1 0 0.9 1 1 0.8 the MAX17480 stores the boot vid when pwrgd first goes high. the stored boot vid is cleared by a rising shdn signal. 9 out3 feedback input for smps3. a 20 discharge fet is enabled from out3 to pgnd when smps3 is shut down. 10 agnd analog ground 11 svd serial vid data 12 svc serial vid clock 13 v ddio cpu i/o voltage (1.8v or 1.5v). logic thresholds for svd and svc are relative to the voltage at v ddio . 14 gnds2 smps2 remote ground-sense input. normally connected to gnd directly at the load. gnds2 internally connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage drops from the smps ground to the load ground. connect gnds1 or gnds2 above 0.9v combined-mode operation (unified core). when gnds2 is pulled above 0.9v, gnds1 is used as the remote ground-sense input.
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 17 pin description (continued) pin name function 15 fbac2 output of the voltage-positioning transconductance amplifier for smps2. the rc network between this pin and the positive side of the remote-sensed output voltage sets the transient ac droop: where r droop_ac2 is the transient (ac) voltage-positioning slope that provides an acceptable trade-off between stability and load-transient response, g m(fbac2) = 2ms (typ), and r sense2 is the value of the current-sense element that is used to provide the (csp2, csn2) current-sense voltage, z cfb2 is the impedance of c fb2 , and fbac2 is high impedance in shutdown. 16 fbdc2 feedback-sense input for smps2. connect a resistor r fbdc2 between fbdc2 and the positive side of the feedback remote sense, and a capacitor from fbac2 to couple the ac ripple from fbac2 to fbdc2. an integrator on fbdc2 corrects for output ripple and ground-sense offset. to enable a dc load-line less than the ac load-line, add a resistor from fbac2 to fbdc2. to enable a dc load-line equal to the ac load-line, short fbac2 to fbdc2. see the core steady- state voltage positioning (dc droop) section. fbdc2 is high impedance in shutdown. 17 csn2 negative current-sense input for smps2. connect to the negative side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. a 20 discharge fet is enabled from csn2 to pgnd when the smps2 is shut down. 18 csp2 positive current-sense input for smps2. connect to the positive side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. 19 pgd_in system power-good input pgd_in is low when shdn first goes high. the MAX17480 decodes the two svi bits to determine the boot voltage. the svi bits can be changed dynamically during this time while pgd_in remains low and pwrgd is still low. pgd_in goes high after the MAX17480 reaches the boot voltage. this indicates that the svi block is active, and the MAX17480 starts to respond to the svi commands. the MAX17480 stores the boot vid when pwrgd first goes high. the stored boot vid is cleared by rising shdn . after pgd_in has gone high, if at any time pgd_in goes low, the MAX17480 regulates to the previously stored boot vid. the slew rate during this transition is set by the resistor between the time and gnd pins. pwrgd follows the blanking for normal vid transition. the subsequent rising edge of pgd_in does not change the stored vid. r rr rrr droop ac fbac fbdc fbac fbdc fb _2 22 222 = ++ z z rg cfb sense m fbac 2 22 ()
MAX17480 amd 2-/3-output mobile serial vid controller 18 ______________________________________________________________________________________ pin description (continued) pin name function 20 pwrgd open-drain power-good output. pwrgd is the wired-or open-drain output of all three smps outputs. pwrgd is forced high impedance whenever the slew-rate controller is active (output voltage transitions). during startup, pwrgd is held low for an additional 20s after the MAX17480 reaches the startup boot voltage set by the svc and svd pins. the MAX17480 stores the boot vid when pwrgd first goes high. the stored boot vid is cleared by rising shdn . pwrgd is forced low in shutdown. when smps is in pulse-skipping mode, the upper pwrgd threshold comparator for the respective smps is blanked during a downward vid transition. the upper pwrgd threshold comparator is re- enabled once the output is in regulation (figure 6). 21 dh2 smps2 high-side gate-driver output. dh2 swings from lx2 to bst2. low in shutdown. 22 lx2 smps2 inductor connection. lx2 is the internal lower supply rail for the dh2 high-side gate driver. also used as an input to smps2s zero-crossing comparator. 23 bst2 boost flying capacitor connection for the dh2 high-side gate driver. an internal switch between v dd and bst2 charges the flying capacitor during the time the low-side fet is on. 24 dl2 smps2 low-side gate-driver output. dl2 swings from gnd2 to v dd . dl2 is forced low in shutdown. dl2 is also forced high when an output overvoltage fault is detected. dl2 is forced low in skip mode after an inductor current zero crossing (gnd2 - lx2) is detected. 25 v dd supply voltage input for the dl_ drivers. v dd is also the supply voltage used to internally recharge the bst_ flying capacitors during the off-time. connect v dd to the 4.5v to 5.5v system supply voltage. bypass v dd to gnd with a 2.2f or greater ceramic capacitor. 26 dl1 smps1 low-side gate-driver output. dl1 swings from gnd1 to v dd . dl1 is forced low in shutdown. dl1 is also forced high when an output overvoltage fault is detected. dl1 is forced low in skip mode after an inductor current zero crossing (gnd1 - lx1) is detected. 27 bst1 boost flying capacitor connection for the dh1 high-side gate driver. an internal switch between v dd and bst1 charges the flying capacitor during the time the low-side fet is on. 28 lx1 smps1 inductor connection. lx1 is the internal lower supply rail for the dh1 high-side gate driver. also used as an input to smps1s zero-crossing comparator. 29 dh1 smps1 high-side gate-driver output. dh1 swings from lx1 to bst1. low in shutdown. 30 vrhot active-low open-drain output of internal comparator. vrhot is pulled low when the voltage at thrm goes below 1.5v (30% of v cc ). vrhot is high impedance in shutdown. 31 thrm input of internal comparator. connect the output of a resistor- and thermistor-divider (between v cc and gnd) to thrm. select the components so the voltage at thrm falls below 1.5v (30% of v cc ) at the desired high temperature. 32 v cc controller supply voltage. connect to a 4.5v to 5.5v source. bypass to gnd with a 1f minimum capacitor. a v cc uvlo event that occurs while the ic is functioning is latched, and can only be cleared by cycling v cc power or by toggling shdn .
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 19 pin description (continued) pin name function 33 csp1 positive current-sense input for smps1. connect to the positive side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is ut ilized for current sensing. 34 csn1 negative current-sense input for smps1. connect to the negative side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is ut ilized for current sensing. a 20 discharge fet is enabled from csn1 to pgnd when the smps1 is shut down. 35 fbdc1 feedback sense input for smps1. connect a resistor r fbdc1 between fbdc1 and the positive side of the feedback remote sense, and a capacitor from fbac1 to couple the ac ripple from fbac1 to fbdc1. an integrator on fbdc1 corrects for output ripple and ground-sense offset. to enable a dc load-line less than the ac load-line, add a resistor from fbac1 to fbdc1. to enable a dc load-line equal to the ac load-line, short fbac1 to fbdc1. see the core steady- state voltage positioning (dc droop) section. fbdc1 is high impedance in shutdown. 36 fbac1 output of the ac voltage-positioning transconductance amplifier for smps1. the rc network between this pin and the positive side of the remote-sensed output voltage sets the transient ac droop: where r droop_ac1 is the transient (ac) voltage-positioning slope that provides an acceptable trade-off between stability and load-transient response, g m(fbac1) = 2ms (typ), r sense1 is the value of the current-sense element that is used to provide the (csp1, csn1) current-sense voltage, z cfb1 is the impedance of c fb1 , and fbac1 is high impedance in shutdown. 37 gnds1 smps1 remote ground-sense input. normally connected to gnd directly at the load. gnds1 internally connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage drops from the smps ground to the load ground. connect gnds1 or gnds2 above 0.9v combined-mode operation (unified core). when gnds1 is pulled above 0.9v, gnds2 is used as the remote ground-sense input. 38 option four-level input to enable offset and change core smps address when offset is enabled, the MAX17480 enables a fixed +12.5mv offset on smps1 and smps2 vid codes after pgd_in goes high. this configuration is intended for applications that implement a load line. an external resistor at fbdc_ sets the load-line. the offset can be disabled by setting the psi_l bit to 0 through the serial interface. additionally, the option level also allows core smps1 and smps2 to take on either the vdd0 or vdd1 addresses. vdd0 refers to core0, and vdd1 refers to core1 for the amd cpu. the nb smps is not affected by the option setting. option offset enabled smps1 address smps2 address v cc 0 bit 1 (vdd0) bit 2 (vdd1) 3.3v 0 bit 2 (vdd1) bit 1 (vdd0) 2v 1 bit 1 (vdd0) bit 2 (vdd1) gnd 1 bit 2 (vdd1) bit 1 (vdd0) r rr rrr droop ac fbac fbdc fbac fbdc fb _1 11 111 = ++ z z rg cfb sense m fbac 1 11 ()
MAX17480 amd 2-/3-output mobile serial vid controller 20 ______________________________________________________________________________________ pin description (continued) pin name function 39 osc oscillator adjustment input. connect a resistor (r osc ) between osc and gnd to set the switching frequency (per phase): f osc = 300khz x 143k /r osc a 71.4k to 432k resistor corresponds to switching frequencies of 600khz to 100khz, respectively, for smps1 and smps2. smps3 runs at twice the programmed switching frequency. switching frequency selection is limited by the minimum on-time. see the core switching frequency description in the smps design procedure section. 40 time slew-rate adjustment pin. the total resistance r time from time to gnd sets the internal slew rate: pwm slew rate = (6.25mv/s) x (143k /r time ) where r time is between 35.7k and 357k . this slew rate applies to both upward and downward vid transitions, and to the transition from boot mode to vid mode. downward vid transition slew rate in skip mode can appear slower because the output transition is not forced by the smps. the slew rate for startup is fixed at 1mv/s. ep pgnd exposed pad. power ground connection and source connection of the internal low-side mosfet.
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 21 component v in = 7v to 24v, v out1 = v out2 = 1.0v to 1.3v, 18a per phase v in3 = 5v, v out3 = 1.0v to 1.3v, 4a v in = 4.5v to 14v, v out1 = v out2 = 1.0v to 1.3v, 18a per phase v in3 = 3.3v, v out3 = 1.0v to 1.3v, 4a mode separate, 2-phase mobile (gnds1 = gnds2 = low) separate, 2-phase mobile (gnds1 = gnds2 = low) switching frequency 300khz 600khz 500khz 1mhz c in_ input capacitor (2) 10f, 25v taiyo yuden tmk432bj106km (1) 10f, 6.3v tdk c2012x5r0j106m taiyo yuden jmk212bj106m (2) 10f, 16v taiyo yuden tmk432bj106km (1) 10f, 6.3v tdk c2012x5r0j106m taiyo yuden jmk212bj106m c out_ output capacitor (2) 330f, 2v, 6m , low-esr capacitor panasonic eefsx0d331xe sanyo 2tpe330m6 (1) 220f, 2v, 6m , low-esr capacitor panasonic eefsd0d221r sanyo 2tpe220m6 (2) 220f, 2v, 6m , low-esr capacitor panasonic eefsd0d221r sanyo 2tpe220m6 (1) 47f, ceramic capacitor n h_ high-side mosfet (1) vishay/siliconix si7634dp none (1) international rectifier irf7811w none n l_ low-side mosfet (2) vishay/siliconix si7336adp none (2) vishay/siliconix si7336adp none d l_ schottky rectifier (if needed) 3a, 40v schottky diode central semiconductor cmsh3-40 none 3a, 40v schottky diode central semiconductor cmsh3-40 none l_ inductor 0.45h, 21a, 1.1m power inductor panasonic etqp4lr45wfc 1.5h, 5a, 21m power inductor nec/tokin mplch0525lir5 toko fdv0530-1r5m 0.36h, 21a, 1.1m power inductor panasonic etqp4lr36wfc 0.6h, 4.95a, 16m power inductor sumida cdr6d23mn table 1. component selection for standard applications note: mobile applications should be designed for separate mode operation. component selection is dependent on amd cpu ac and dc specifications. manufacturer website avx corporation www.avxcorp.com bi technologies www.bitechnologies.com central semiconductor corp. www.centralsemi.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com kemet corp. www.kemet.com nec tokin america, inc. www.nec-tokinamerica.com panasonic corp. www.panasonic.com manufacturer website pulse engineering www.pulseeng.com renesas technology corp. www.renesas.com sanyo electric co., ltd. www.sanyodevice.com siliconix (vishay) www.vishay.com sumida corp. www.sumida.com taiyo yuden www.t-yuden.com tdk corp. www.component.tdk.com toko america, inc. www.tokoam.com table 2. component suppliers standard application circuit the MAX17480 standard application circuit (figure 2) generates two independent 18a outputs and one 4a output for amd mobile cpu applications. see table 1 for component selections. table 2 lists the component manufacturers.
MAX17480 amd 2-/3-output mobile serial vid controller 22 ______________________________________________________________________________________ MAX17480 n l1 d l1 n h1 39 osc 13 v ddio 12 svc 11 svd 40 time 27 bst1 29 dh1 28 lx1 26 dl1 32 v cc 25 v dd c lx1 c dcr1 csp1 r ilim2 r osc 1 ilim12 r vcc 10 ? r csp1 csp1 +5v csn1 r csn1 2x 100k ? r ntc r ilim1 r lx1 r dcr1 c vcc 2.2 f c bst1 0.22 f 33 csp1 34 csn1 c cs1 c vdd 1 f c csn1 agnd c in1 c out1 2x 330 f 6m ? pwr v in 4v to 26v l1 0.45 h l2 0.45 h pwr pwr pwr csn1 v out1 /18a tdc r fbac1 2k ? r fbdc1 2k ? 36 fbac1 35 fbdc1 c fb1 2200pf n l2 d l2 n h2 23 bst2 21 dh2 22 lx2 24 dl2 c lx2 c dcr2 csp2 r lx2 r dcr2 c bst2 0.22 f c in2 c out2 2x 330 f 6m ? pwr v in 4v to 26v pwr pwr pwr pwr pwr pwr csn2 v out2 /18a tdc r csp2 csp2 csn2 core0 sense_h r csn2 18 csp2 17 csn2 c cs2 c csn2 agnd agnd 1.5v or 1.8v 19 pgd_in system power-good 3, 4 in3 5, 6 lx3 7 bst3 v in_nb 2.7v to 5.5v 2 ilim3 v cc +3.3v v cc v out3 /4a 8 shdn 20 pwrgd 30 vrhot 31 thrm agnd 38 option serial input core0 sense_l 100 ? 37 gnds1 4700pf agnd 4700pf agnd core0 18a regulator core1 18a regulator 100 ? r fbac2 2k ? r fbdc2 2k ? 15 fbac2 16 fbdc2 c fb2 2200pf core1 sense_h power ground analog ground core1 sense_l 100 ? 14 gnds2 4700pf agnd 4700pf agnd 100 ? ep = pgnd on off offset option bit1 (vdd0) bit2 (vdd1) bit1 (vdd0) bit2 (vdd1) 0 0 1 1 v cc 3.3v 2v gnd bit2 (vdd1) bit1 (vdd0) bit2 (vdd1) bit1 (vdd0) smps1 addr smps2 addr i lx3_pk (a) ilim3 +12.5 +12.5 4-level ilim3 5.25 4.25 v cc gnd smps3 offset (mv) r thrm nb sense_h 9 out3 10 agnd 0 ? c in_nb 4700pf c bst3 0.1 f c out3 220 f 6m ? l3 1.5 h agnd agnd internal 4a nb regulator figure 2. griffin/puma standard application circuit
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 23 MAX17480 n l1 d l1 n h1 39 osc 13 v ddio 12 svc 11 svd 40 time 27 bst1 29 dh1 28 lx1 26 dl1 32 v cc 25 v dd c lx1 c dcr1 csp1 r ilim2 r osc 1 ilim12 r vcc 10 ? r csp1 csp1 +5v csn1 r csn1 2x 100k ? r ntc r ilim1 r lx1 r dcr1 c vcc 2.2 f c bst1 0.22 f 33 csp1 34 csn1 c cs1 c vdd 1 f c csn1 agnd c in1 c out 3x330 f 6m ? pwr v in 4v to 26v l1 0.45 h l2 0.45 h pwr pwr pwr csn1 v core /36a tdc r fbac1 2k ? r fbdc1 2k ? 36 fbac1 35 fbdc1 c fb1 2200pf n l2 d l2 n h2 23 bst2 21 dh2 22 lx2 24 dl2 c lx2 c dcr2 csp2 r lx2 r dcr2 c bst2 0.22 f c in2 pwr v in 4.5v to 28v pwr pwr pwr pwr pwr csn2 r csp2 csp2 csn2 core0 sense_h r csn2 18 csp2 17 csn2 c cs2 c csn2 agnd agnd 1.5v or 1.8v 19 pgd_in system power-good 3, 4 in3 5, 6 lx3 7 bst3 v in_nb 2.7v to 5.5v 2 ilim3 v cc +3.3v v cc v out3 /4a 8 shdn 20 pwrgd 30 vrhot 31 thrm agnd 38 option serial input core0 sense_l 100 ? 37 gnds1 4700pf agnd 4700pf agnd 36a core regulator 100 ? r fbac2 2k ? r fbdc2 2k ? 15 fbac2 16 fbdc2 c fb2 2200pf v core power ground analog ground v ddio 14 gnds2 4700pf agnd 100 ? ep = pgnd on off offset option bit1 (vdd0) bit2 (vdd1) bit1 (vdd0) bit2 (vdd1) 0 0 1 1 v cc open ref gnd bit2 (vdd1) bit1 (vdd0) bit2 (vdd1) bit1 (vdd0) smps1 addr smps2 addr i lx3_pk (a) ilim3 +12.50 +12.50 4-level ilim3 5.25 4.25 v cc gnd smps3 offset (mv) r thrm nb sense_h 9 out3 10 agnd 100 ? c in_nb 4700pf c bst3 0.1 f c out3 220 f 6m ? l3 1.5 h agnd agnd internal 4a nb regulator connect gnds2 to v ddio for unified core operation figure 3. caspian/tigris standard application circuit
MAX17480 amd 2-/3-output mobile serial vid controller 24 ______________________________________________________________________________________ dac1 uvlo refok run agnd ref (2.0v) addr svc svd svi interface pgd_in shdn v ddio dac2 dac3 fault2 fault1 dacout1 dacout2 v ddio v cc ofs_en option 4-level decode addr ofs_en ilim12 current limit x2 imax_ imin_ csa_ ref skip_ gnds1 blank1 target1 gnds2 blank2 target2 blank3 target3 dacout3 osc time gnds2 gnds1 smps1 fault block smps2 fault block smps3 fault block pgd1 fault1 fbdc1 target1 blank1 pgd2 fault2 fbdc2 target2 blank2 pgd3 fault3 out3 target3 blank3 in3 lx3 pgnd bst3 ilim3 pwr target3 out3 smps3 driver block skip3 combine detect combine clock2 clock1 i slope1 i slope2 clock3 i slope3 csp_ csn_ fbdc_ smps1 and smps2 pwm block smps1 and smps2 driver block fbac_ x2 pwm_ clock_ target_ imin_ imax_ skip_ i slope_ csa_ combine pwm_ bst_ v dd dh_ lx_ pgnd dl_ x2 skip_ vrhot thrm 0.3 x v cc gnds mux pwrgd csp3 csn3 fault3 smps1 target and slew rate block smps2 target and slew rate block smps3 target and slew rate block pwr MAX17480 7-bit vid skip1 7-bit vid skip2 7-bit vid skip3 oscillator figure 4. functional diagram
MAX17480 detailed description the MAX17480 consists of a dual fixed-frequency pwm controller with external switches that generate the sup- ply voltage for two independent cpu cores and one low-input-voltage internal switch smps for the separate nb smps. the cpu core smpss can be configured as independent outputs, or as a combined output by con- necting the gnds1 or gnds2 pin-strap high (gnds1 or gnds2 pulled to 1.5v to 1.8v, which are the respec- tive voltages for ddr3 and ddr2). all three smpss can be programmed independently to any voltage in the vid table (see table 4) using the serial vid interface (svi). the cpu is the svi bus master, while the MAX17480 is the svi slave. voltage transitions are commanded by the cpu as a single step command from one vid code to another. the MAX17480 slews the smps outputs at the slew rate programmed by the exter- nal r time resistor during vid transitions and the transi- tion from boot mode to vid mode. during startup, the MAX17480 smpss are always in pulse-skipping mode. after exiting the boot mode, the individual psi_l bit sets the respective smps into pulse-skipping mode or forced-pwm mode, depending on the system power state, and adds the +12.5mv off- set for core supplies if enabled by the option pin. in combined mode, the psi_l bit adds the +12.5mv offset if enabled by the option pin, and switches from 1-phase pulse-skipping mode to 2-phase pwm mode. figure 4 is the MAX17480 functional diagram. +5v bias supply (v cc , v dd ) the MAX17480 requires an external 5v bias supply in addition to the battery. typically, this 5v bias supply is the notebooks main 95%-efficient 5v system supply. keeping the bias supply external to the ic improves efficiency and eliminates the cost associated with the 5v linear smps that would otherwise be needed to sup- ply the pwm circuit and gate drivers. the 5v bias supply powers both the pwm controller and internal gate-drive power, so the maximum current drawn is: i bias = i cc + f sw_core q g_core + f sw_nb q g_nb = 50ma to 70ma (typ) where i cc is provided in the electrical characteristics table, f sw_core and f sw_nb are the respective core and nb smps switching frequencies, q g_core is the gate charge of the external mosfets as defined in the mosfet data sheets, and q g_nb is approximately 2nc. if the +5v bias supply is powered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensure startup. switching frequency (osc) connect a resistor (r osc ) between osc and gnd to set the switching frequency (per phase): f sw = 300khz 143k ? /r osc a 71.4k ? to 432k ? resistor corresponds to switching fre- quencies of 600khz to 100khz, respectively, for the core smpss, and 1.2mhz to 200khz for the nb smps. high- frequency (600khz) operation for the core smps opti- mizes the application for the smallest component size, trading off efficiency due to higher switching losses. this might be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low-frequency (100khz) operation offers the best overall efficiency at the expense of component size and board space. the nb smps runs at twice the switching frequency of the core smpss. the low power of the nb rail allows for higher switching frequencies with little impact on the overall efficiency. minimum on-time (t on(min) ) must be taken into consid- eration when selecting a switching frequency. see the core switching frequency description in the smps design procedure section. interleaved multiphase operation the MAX17480 interleaves both core smpss phases resulting in 180 out-of-phase operation that minimizes the input and output filtering requirements, reduces electromagnetic interference (emi), and improves effi- ciency. the high-side mosfets do not turn on simulta- neously during normal operation. the instantaneous input current is effectively reduced by the number of active phases, resulting in reduced input-voltage ripple, effective series resistance (esr) power loss, and rms ripple current (see the core input capacitor selection section). therefore, the controller achieves high perfor- mance while minimizing the component countwhich reduces cost, saves board space, and lowers compo- nent power requirementsmaking the MAX17480 ideal for high-power, cost-sensitive applications. amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 25
MAX17480 amd 2-/3-output mobile serial vid controller 26 ______________________________________________________________________________________ transient phase repeat when a transient occurs, the output voltage deviation depends on the controllers ability to quickly detect the transient and slew the inductor current. a fixed-frequency controller typically responds only when a clock edge occurs, resulting in a delayed transient response. to minimize this delay time, the MAX17480 includes enhanced transient detection and transient phase repeat capabilities. if the controller detects that the out- put voltage has dropped by 41mv, the transient detec- tion comparator immediately retriggers the phase that completed its on-time last. the controller triggers the subsequent phases as normal, on the appropriate oscillator edges. this effectively triggers a phase a full cycle early, increasing the total inductor-current slew rate and providing an immediate transient response. core smps feedback adjustment amplifiers the MAX17480 provides an fbac and fbdc pin for each smps to allow for flexible ac and dc droop set- tings. fbac is the output of an internal transconduc- tance amplifier that outputs a current proportional to the current-sense signal. fbdc is the feedback input that is compared against the internal target. place resistors and capacitors at the fbac and fbdc pins as shown in figure 5. with this configuration, the dc droop is always less than or equal to the ac droop. core steady-state voltage positioning (dc droop) fbdc is the feedback input to the error amplifier. based on the configuration in figure 5, the core smps output voltage is given by: where the target voltage (v target ) is defined in the nominal output-voltage selection section, and the fbac amplifiers output current (i fbac ) is determined by each phases current-sense voltage: where v cs = v csp - v csn is the differential current-sense voltage, and g m (fbac) is typically 2ms as defined in the electrical characteristics table. dc droop is typically used together with the +12.5mv offset feature to keep within the dc tolerance window of the application. see the offset and address change for core smpss (option) section. the ripple voltage on fbdc must be less than the -33mv (max) transient phase repeat threshold: where ? i l is the inductor ripple current, r esr is the effective output esr at the remote sense point, r sense is the current-sense element, and g m (fbac) is 2.06ms (max) as defined in the electrical characteristics table. the worst-case inductor ripple occurs at the maximum input-voltage and maximum output-voltage conditions: to make the dc and ac load-lines the same, directly short fbac to fbdc. to disable dc voltage positioning, remove r fb , which connects fbac to fbdc. core transient voltage-positioning amplifier (ac droop) each of the MAX17480 core supply smpss includes one transconductance amplifier for voltage positioning. the amplifiers inputs are generated by summing their respec- tive current-sense inputs, which differentially sense the voltage across either current-sense resistor or the induc- tors dcr. the voltage-positioning droop amplifiers output (fbac) connects to the remote-sense point of the output through an rc network that sets each phases ac volt- age-positioning gain: where the target voltage (v target ) is defined in the nominal output-voltage selection section, z cfb is the effective impedance of c fb , and the fbac amplifiers output current (i fbac ) is determined by each phases current-sense voltage: vv rr rr rz out target fbac fbdc fbac fbdc fb cf =? ++ b b fbdc i ? i vvv v lmax out max in max out max in m () () () () ( = ? () a ax sw fl ) ? r mv i r r r fbdc l esr fbac f 66 ? () + ( b b fbac l sense m fbac rirg mv ) () ?? 66 r rrr ir g r fbac fbac fbdc fb l sense m fbac fbdc ++ + ? () ? ? ir mv l esr 2 33 igv fbac m fbac cs = () vv rr rrr i out target fbdc fbac fbac fbdc fb fb =? ++ a ac r fbac r fbdc fbac csp csn g m(fbac) error amp fbdc c fb 4700pf core sense_h agnd 100 ? target r fb MAX17480 figure 5. core smps feedback connection
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 27 where v cs = v csp - v csn is the differential current- sense voltage, and g m (fbac) is 2.06ms (max) as defined in the electrical characteristics table. ac droop is required for stable operation of the MAX17480. a minimum of 1.5mv/a is recommended. ac droop must not be disabled. core differential remote sense the MAX17480 controller includes independent differen- tial, remote-sense inputs for each cpu core to eliminate the effects of voltage drops along the pcb traces and through the processors power pins. the feedback-sense (fbdc_) input connects to the remote-sensed output through the resistance at fbdc_ (r fbdc_ ). the ground- sense (gnds_) input connects to an amplifier that adds an offset directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. connect the feedback- sense (fbdc_) r fbdc_ resistor and ground-sense (gnds_) input directly to the respective cpu cores remote- sense outputs as shown in figure 2. gnds1 and gnds2 are dual-function pins. at power-on, the voltage levels on gnds1 and gnds2 configure the MAX17480 as two independent switching smpss, or one higher current 2-phase smps. keep both gnds1 and gnds2 low during power-up to configure the MAX17480 in separate mode. connect gnds1 or gnds2 to a volt- age above 0.8v (typ) for combined-mode operation. in the amd mobile system, this is automatically done by the cpu that is plugged into the socket that pulls gnds1 or gnds2 the v ddio voltage level. when gnds1 is pulled high to indicate combined- mode operation, the remote ground sense is automati- cally switched to gnds2. when gnds2 is pulled high to indicate combined-mode operation, the remote ground sense is automatically switched to gnds1. gnds1 and gnds2 do not dynamically switch in the real application. it is only switched when one cpu is removed (e.g., split-core cpu), and another is plugged in (e.g., combined-core cpu). this should not be done when the socket is hot (i.e., powered). the MAX17480 checks the gnds1 and gnds2 levels at the time when the internal refok signal goes high, and latches the operating mode information (separate or combined mode). this latch is cleared by cycling the shdn pin. core integrator amplifier an internal integrator amplifier forces the dc average of the fbdc_ voltage to equal the target voltage. this transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (figure 4), allowing accurate dc output-voltage regulation regardless of the output ripple voltage. the MAX17480 disables the integrator during down- ward vid transitions done in pulse-skipping mode. the integrator remains disabled until the transition is com- pleted (the internal target settles) and the output is in regulation (edge detected on the error comparator). the integrator amplifier can shift the output voltage by 80mv (min). the maximum difference between tran- sient ac droop and dc droop should not exceed 80mv at the maximum allowed load current to guaran- tee proper dc output-voltage accuracy over the full load conditions. nb smps feedback adjustment amplifiers nb steady-state voltage positioning (dc droop) the nb smps has a built-in load-line that is -5.5mv/a. the output peak voltage (v out3_pk+ ) is set to: where the target voltage (v target3 ) is defined in the nominal output-voltage selection section, f sw3 is the nb switching frequency, and i load3 is the output load current of the nb smps. 2-wire serial interface (svc, svd) the MAX17480 supports the 2-wire, write-only, serial- interface bus as defined by the amd serial vid inter- face specification. the serial interface is similar to the high-speed 3.4mhz i 2 c bus, but without the master mode sequence. the bus consists of a clock line (svc) and a data line (svd). the cpu is the bus master, and the MAX17480 is the slave. the MAX17480 serial inter- face works from 100khz to 3.4mhz. in the amd mobile application, the bus runs at 3.4mhz. the serial interface is active only after pgd_in goes high in the startup sequence. the cpu sets the vid voltage of the three internal dacs and the psi_l bit through the serial interface. during the startup sequence, the svc and svd inputs serve an alternate function to set the 2-bit boot vid for all three dacs while pwrgd is low. v v mv/a (i i out3_pk target3 load3 l =?+ 55 3 2 .) ? ? i l 3 3 = ? () vv v lv f in out out in sw 33 3 33 3 igv fbac m fbac cs = ()
MAX17480 amd 2-/3-output mobile serial vid controller 28 ______________________________________________________________________________________ nominal output-voltage selection core smps output voltage the nominal no-load output voltage (v target ) for each smps is defined by the selected voltage reference (vid dac) plus the remote ground-sense adjustment (v gnds ) and the offset voltage (v offset ) as defined in the following equation: where v dac is the selected vid voltage of the core smps dac, v gnds is the ground-sense correction volt- age for core supplies, and v offset is the +12.5mv off- set enabled by the option pin when the psi_l is set high for core supplies. nb smps output voltage the nominal output voltage (v target ) for the nb is defined by the selected voltage reference (vid dac) plus the offset voltage (v offset_nb ) as defined in the following equation: where v dac is the selected vid voltage of the nb dac, and v offset_nb is +12.5mv. 7-bit dac inside the MAX17480 are three 7-bit digital-to-analog converters (dacs). each dac can be individually pro- grammed to different voltage levels by the serial-inter- face bus. the dac sets the target for the output voltage for the core and nb smpss. the available dac codes and resulting output voltages are compatible with the amd svi (table 4) specifications. boot voltage on startup, the MAX17480 slews the target for all three dacs from ground to the boot voltage set by the svc and svd pin-voltage levels. while the output is still below regulation, the svc and svd levels can be changed, and the MAX17480 sets the dacs to the new boot volt- age. once the programmed boot voltage is reached and pwrgd goes high, the MAX17480 stores the boot vid. changes in the svc and svd settings do not change the output voltage once the boot vid is stored. when pgd_in goes high, the MAX17480 exits boot mode, and the three dacs can be independently set to any voltage in the vid table by the serial interface. if pgd_in goes from high to low any time after the boot vid is stored, the MAX17480 sets all three dacs back to the voltage of the stored boot vid. table 3 is the boot voltage code table. core smps offset a +12.5mv offset can be added to both core smps dac voltages for applications that include dc droop. the offset is applied only after the MAX17480 exits boot mode (pgd_in going from low to high), and the MAX17480 enters the serial-interface mode. the offset is disabled when the psi_l bit is set, saving more power when the load is light. the option pin setting enables or disables the +12.5mv offset. connect option to osc (2v) or gnd to enable the offset. keep option connected to 3.3v or v cc to disable the offset. see the offset and address change for core smpss (option) section. nb smps offset the nb smps output has a -5.5mv/a load line. a +12.5mv offset is added to keep the output within regu- lation over the full load. see the offset and current- limit setting for nb smps (ilim3) section. output-voltage transition timing smps output-voltage transition the MAX17480 performs positive voltage transitions in a controlled manner, automatically minimizing input surge currents. this feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in- time arrival at the new output-voltage level with the low- est possible peak currents for a given output capacitance. the slew rate (set by resistor r time ) must be set fast enough to ensure that the transition is com- pleted within the maximum allotted time for proper cpu operation. r time is between 35.7k ? and 357k ? for cor- responding slew rates between 25mv/s to 2.5mv/s, respectively, for the smpss. at the beginning of an output-voltage transition, the MAX17480 blanks both pwrgd comparator thresholds, preventing the pwrgd open-drain output from chang- ing states during the transition. at the end of an upward vid transition, the controller enables both pwrgd thresholds approximately 20s after the slew-rate controller reaches the target output voltage. at the end vvvv target out dac offset nb 33 ==+ _ vvvvv target fbdc dac gnds offset ==++ svc svd boot voltage v out (v) 0 0 1.1 0 1 1.0 1 0 0.9 1 1 0.8 table 3. boot voltage code table
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 29 of a downward vid transition, the upper pwrgd thresh- old is enabled only after the output reaches the lower vid code setting. figure 6 shows vid transition timing. the MAX17480 automatically controls the current to the minimum level required to complete the transition in the calculated time. the slew-rate controller uses an inter- nal capacitor and current source programmed by r time to transition the output voltage. the total transi- tion time depends on r time , the voltage difference, and the accuracy of the slew-rate controller (c slew accuracy). the slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit set by ilim12 for the core smpss and ilim3 for the nb smps. for all dynamic positive vid transitions or negative vid transitions in forced- pwm mode (psi_l set to 1), the transition time (t tran ) is given by: where dv target /dt = 6.25mv/s 143k ? /r time is the slew rate, v old is the original output voltage, and v new is the new target voltage. see the slew-rate accuracy in the electrical characteristics table for slew-rate limits. the output voltage tracks the slewed target voltage, making the transitions relatively smooth. the average inductor current per phase required to make an output voltage transition is: where dv target /dt is the required slew rate and c out is the total output capacitance of each phase. if the smps is in a pulse-skipping mode (psi_l set to 0), the discharge rate of the output voltage during downward transitions is then dependent on the load current and total output capacitance for loads less than a minimum current, and dependent on the r time pro- grammed slew rate for heavier loads. the critical load current (i load(crit) ) where the transition time is depen- dent on the load is: for load currents less than i load(crit) , the transition time is: for soft-start, the controller uses a fixed slew rate of 1mv/s. in shutdown, the outputs are discharged using a 20 ? switch through the csn_ pins for the core smpss and through the out3 pin for the nb smps. forced-pwm operation after exiting the boot mode and if the psi_l bit is set to 1, the MAX17480 operates with the low-noise, forced- pwm control scheme. forced-pwm operation disables the zero-crossing comparator, forcing the low-side gate-drive waveforms to constantly be the complement of the high-side gate-drive waveforms. this keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging the output capacitors. forced-pwm operation comes at a cost: the no-load +5v bias supply current remains between 50ma to 70ma, t cdv i tran out target load ? icdvdt load crit out target () / ? () ic dv dt l out target ? () / t vv dv dt tran new old target = ? ? ? ? ? () / smps voltage (smps target) pwrgd smps load light load heavy load svc/svd bus idle bus idle bus idle pwrgd upper threshold pwrgd lower threshold smps target upper threshold blanked blank high-z blank high-z blank high-z 20 figure 6. vid transition timing
MAX17480 amd 2-/3-output mobile serial vid controller 30 ______________________________________________________________________________________ depending on the external mosfets and switching fre- quency. to maintain high efficiency under light load conditions, the processor could switch the controller to a low-power pulse-skipping control scheme. pulse-skipping operation during soft-start and in power-saving modewhen the psi_l bit is set to 0the MAX17480 operates in pulse- skipping mode. pulse-skipping mode enables the drivers zero-crossing comparator, so the driver pulls its dl low when zero inductor current is detected (v gnd - v lx = 0). this keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light load conditions to avoid overcharging the output. in pulse-skipping operation, the controller terminates the on-time when the output voltage exceeds the feed- back threshold and when the current-sense voltage exceeds the idle-mode current-sense threshold (v idle = 0.15 x v limit for the core smps and i lx3min = 0.25 x i lx3pk setting for the nb smps). under heavy load conditions, the continuous inductor current remains above the idle-mode current-sense threshold, so the on-time depends only on the feedback voltage thresh- old. under light load conditions, the controller remains above the feedback voltage threshold, so the on-time duration depends solely on the idle-mode current- sense threshold, which is approximately 15% of the full- load peak current-limit threshold set by ilim12 for the core smpss and 25% of the full-load peak current-limit threshold set by ilim3 for the nb smps. during downward vid transitions, the controller tem- porarily sets the ovp threshold of the smpss to 1.85v (typ), preventing false ovp faults. once the error ampli- fier detects that the output voltage is in regulation, the ovp threshold tracks the selected vid dac code. each smps can be individually set to operate in pulse- skipping mode when its psi_l bit is set to 0, or set to oper- ate in forced-pwm mode when its psi_l bit is set to 1. when the core smpss are configured for combined- mode operation, core supplies operate in 1-phase pulse-skipping mode when psi_l = 0, and core sup- plies are in 2-phase forced-pwm mode when psi_l = 1. idle-mode current-sense threshold the idle-mode current-sense threshold forces a lightly loaded smps to source a minimum amount of power with each on-time since the controller cannot terminate the on-time until the current-sense voltage exceeds the idle-mode current-sense threshold (v idle = 0.15 x v limit for the core smps and i lx3min = 0.25 x i lx3pk setting for the nb smps). since the zero-crossing com- parator prevents the switching smps from sinking current, the controller must skip pulses to avoid over- charging the output. when the clock edge occurs, if the output voltage still exceeds the feedback threshold, the controller does not initiate another on-time. this forces the controller to actually regulate the valley of the out- put voltage ripple under light load conditions. automatic pulse-skipping crossover in skip mode, the MAX17480 zero-crossing compara- tors are active. therefore, an inherent automatic switchover to pfm takes place at light loads, resulting in a highly efficient operating mode. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor currents zero crossing. the drivers zero-crossing comparator senses the inductor current across the low-side mosfet. once v gnd - v lx drops below the zero-crossing threshold, the driver forces dl low. this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current opera- tion (also known as the critical conduction point). the load-current level at which the pfm/pwm crossover occurs, i load(skip) , is given by: the switching waveforms can appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-off in pfm noise vs. light-load efficiency is made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). current sense core smps current sense the output current of each phase is sensed differentially. a low offset voltage and high-gain differential current amplifier at each phase allows low-resistance current- sense resistors to be used to minimize power dissipa- tion. sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flex- ibility of using either a current-sense resistor or the dc resistance of the output inductor. i vvv vf l load skip out in out in sw () = ? () 2
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 31 when using a current-sense resistor for accurate output- voltage positioning, the circuit requires a differential rc filter to eliminate the ac voltage step caused by the equivalent series inductance (l esl ) of the current-sense resistor (see figure 7). the esl-induced voltage step does not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and early current-limit detection. similar to the inductor dcr sensing method above, the rc filters time con- stant should match the l/r time constant formed by the current-sense resistors parasitic inductance: svid[6:0] output voltage (v) svid[6:0] output voltage (v) svid[6:0] output voltage (v) svid[6:0] output voltage (v) 000_0000 1.5500 010_0000 1.1500 100_0000 0.7500 110_0000 0.3500 000_0001 1.5375 010_0001 1.1375 100_0001 0.7375 110_0001 0.3375 000_0010 1.5250 010_0010 1.1250 100_0010 0.7250 110_0010 0.3250 000_0011 1.5125 010_0011 1.1125 100_0011 0.7125 110_0011 0.3125 000_0100 1.5000 010_0100 1.1000 100_0100 0.7000 110_0100 0.3000 000_0101 1.4875 010_0101 1.0875 100_0101 0.6875 110_0101 0.2875 000_0110 1.4750 010_0110 1.0750 100_0110 0.6750 110_0110 0.2750 000_0111 1.4625 010_0111 1.0625 100_0111 0.6625 110_0111 0.2625 000_1000 1.4500 010_1000 1.0500 100_1000 0.6500 110_1000 0.2500 000_1001 1.4375 010_1001 1.0375 100_1001 0.6375 110_1001 0.2375 000_1010 1.4250 010_1010 1.0250 100_1010 0.6250 110_1010 0.2250 000_1011 1.4125 010_1011 1.0125 100_1011 0.6125 110_1011 0.2125 000_1100 1.4000 010_1100 1.0000 100_1100 0.6000 110_1100 0.2000 000_1101 1.3875 010_1101 0.9875 100_1101 0.5875 110_1101 0.1875 000_1110 1.3750 010_1110 0.9750 100_1110 0.5750 110_1110 0.1750 000_1111 1.3625 010_1111 0.9625 100_1111 0.5625 110_1111 0.1625 001_0000 1.3500 011_0000 0.9500 101_0000 0.5500 111_0000 0.1500 001_0001 1.3375 011_0001 0.9375 101_0001 0.5375 111_0001 0.1375 001_0010 1.3250 011_0010 0.9250 101_0010 0.5250 111_0010 0.1250 001_0011 1.3125 011_0011 0.9125 101_0011 0.5125 111_0011 0.1125 001_0100 1.3000 011_0100 0.9000 101_0100 0.5000 111_0100 0.1000 001_0101 1.2875 011_0101 0.8875 101_0101 0.4875 111_0101 0.0875 001_0110 1.2750 011_0110 0.8750 101_0110 0.4750 111_0110 0.0750 001_0111 1.2625 011_0111 0.8625 101_0111 0.4625 111_0111 0.0625 001_1000 1.2500 011_1000 0.8500 101_1000 0.4500 111_1000 0.0500 001_1001 1.2375 011_1001 0.8375 101_1001 0.4375 111_1001 0.0375 001_1010 1.2250 011_1010 0.8250 101_1010 0.4250 111_1010 0.0250 001_1011 1.2125 011_1011 0.8125 101_1011 0.4125 111_1011 0.0125 001_1100 1.2000 011_1100 0.8000 101_1100 0.4000 111_1100 off 001_1101 1.1875 011_1101 0.7875 101_1101 0.3875 111_1101 off 001_1110 1.1750 011_1110 0.7750 101_1110 0.3750 111_1110 off 001_1111 1.1625 011_1111 0.7625 101_1111 0.3625 111_1111 off table 4. output-voltage vid dac codes note: the nb smps output voltage has an offset of +12.5mv.
MAX17480 amd 2-/3-output mobile serial vid controller 32 ______________________________________________________________________________________ where l esl is the equivalent series inductance of the current-sense resistor, r sense is current-sense resis- tance value, and c sense and r eq are the time-con- stant matching components. using the dc resistance (r dcr ) of the output inductor allows higher efficiency. in this configuration, the initial tolerance and temperature coefficient of the inductors dcr must be accounted for in the output-voltage droop-error budget and power monitor. this current- sense method uses an rc filtering network to extract the current information from the output inductor (see figure 7). the time constant of the rc network should match the inductors time constant (l/r dcr ): where c sense and r eq are the time-constant matching components. to minimize the current-sense error due to the current-sense inputs bias current (i csp and i csn ), choose r eq less than 2k ? and use the above equation to determine the sense capacitance (c sense ). choose capacitors with 5% tolerance and resistors with 1% tol- erance specifications. temperature compensation is recommended for this current-sense method. see the core voltage positioning and loop compensation sec- tion for detailed information. additional r lx and c lx are always added between the lx_ and csp_ pins if dcr sensing is used, and they provide additional overdrive to the current-sense signal to improve the noise immunity; otherwise, there might be too much jitter or the system could be unstable. nb smps current sense the nb current sense is achieved by sensing the volt- age across the high-side internal mosfet during the on-time. the current information is computed by dividing the sensed voltage by the mosfets on-resistance, r on(nh3) . l r rc dcr eq sense = l r rc esl sense eq sense = MAX17480 n l d l lx_ dl_ dh_ csp_ csn_ n h c in input (v in ) sense resistor a) output series resistor sensing l c out l esl r sense c eq r eq = l esl r sense r eq c eq MAX17480 n l d l lx_ dl_ dh_ csp_ csn_ n h c in input (v in ) inductor b) lossless inductor dcr sensing for thermal compensation: r2 should consist of an ntc resistor in series with a standard thin-film resistor. c out l r dcr r cs = r dcr r2 r1 + r2 r lx r2 r1 c lx c eq r dcr = + l c eq 1 r1 1 r2 figure 7. current-sense configurations
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 33 combined-mode current balance when the core smpss are configured in combined mode (gnds1 or gnds2 pulled to v ddio ), the MAX17480 current-mode architecture automatically forces the individual phases to remain current bal- anced. smps1 is the main voltage-control loop, and smps2 maintains the current balance between the phases. this control scheme regulates the peak induc- tor current of each phase, forcing them to remain prop- erly balanced. therefore, the average inductor current variation depends mainly on the variation in the current- sense element and inductance value. peak current limit the MAX17480 current-limit circuit employs a fast peak inductor current-sensing algorithm. once the current- sense signal of the smps exceeds the peak current-limit threshold, the pwm controller terminates the on-time. see the core peak inductor current limit (ilim12) sec- tion in the core smps design procedure section. power-up sequence (por, uvlo, pgd_in) power-on reset (por) occurs when v cc rises above approximately 3v, resetting the fault latch and preparing the controller for operation. the v cc undervoltage-lockout (uvlo) circuitry inhibits switching until v cc rises above 4.25v (typ). the controller powers up the reference once the system enables the controller v cc above 4.25v and shdn is driven high. with the reference in regulation, the controller ramps the smps and nb voltages to the boot voltage set by the svc and svd inputs: the soft-start circuitry does not use a variable current limit, so full output current is available immediately. pwrgd becomes high impedance approximately 20s after the smps outputs reach regulation. the boot vid is stored the first time pwrgd goes high. the MAX17480 is in pulse-skipping mode during soft-start. figure 8 shows the MAX17480 startup sequence. t v mv s start boot = () 1/ 20 s 10 s 20 s 7 1234 5 6 8 dc_in v ddio svc/svd gnds1 or gnds2 (vdd_plane_strap) smps v out pwrgd pgd_in reset_l shdn bus idle 2-bit boot vid serial mode blank high-z figure 8. startup sequence
MAX17480 amd 2-/3-output mobile serial vid controller 34 ______________________________________________________________________________________ for automatic startup, the battery voltage should be present before v cc . if the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. the controller remains shut down until the fault latch is cleared by toggling shdn or cycling the v cc power supply below 0.5v. if the v cc voltage drops below 4.25v, the controller assumes that there is not enough supply voltage to make valid decisions and could also result in the stored boot vids being corrupted. as such, the MAX17480 immediately stops switching (dh_ and dl_ pulled low), latches off, and discharges the outputs using the inter- nal 20 ? switches from csn_ to gnd. notes for figure 8: 1) the relationship between dc_in and v ddio is not guaranteed. it is possible to have v ddio powered when dc_in is not powered, and it is possible to have dc_in power up before v ddio powers up. 2) as the v ddio power rail comes within specification, vdd_plane_strap becomes valid and svc and svd are driven to the boot vid value by the processor. the system guarantees that v ddio is in specifica- tion and svc and svd are driven to the boot vid value for at least 10s prior to shdn being asserted to the MAX17480. 3) after shdn is asserted, the MAX17480 samples and latches the vdd_plane_strap level at its gnds1 and gnds2 pins when ref reaches the refok thresh- old, and ramps up the voltage plane outputs to the level indicated by the 2-bit boot vid. the boot vid is stored in the MAX17480 for use when pgd_in deasserts. the MAX17480 soft-starts the output rails to limit inrush current from the dc_in rail. the MAX17480 operates in pulse-skipping mode in the boot mode regardless of psi_l settings. 4) the MAX17480 asserts pwrgd. after pwrgd is asserted and all system-wide voltage planes and free-running clocks are within specification, then the system asserts pgd_in. 5) the processor holds the 2-bit boot vid for at least 10s after pgd_in is asserted. 6) the processor issues the set vid command through svi. 7) the MAX17480 transitions the voltage planes to the set vid. the set vid can be greater than or less than the boot vid voltage. the MAX17480 operates in pulse-skipping mode or forced-pwm mode according to the psi_l setting. 8) the chipset enforces a 1ms delay between pgd_in assertion and reset_l deassertion. pwrgd the MAX17480 features internal power-good fault com- parators for each smps. the outputs of these individual power-good fault comparators are logically ored to drive the gate of the open-drain pwrgd output transistor. each smpss power-good fault comparator has an upper threshold of +200mv (typ) and a lower threshold of -300mv (typ). pwrgd goes low if the output of either smps exceeds its respective threshold. pwrgd is forced low during the startup sequence up to 20s after the output is in regulation. the 2-bit boot vid is stored when pwrgd goes high during the startup sequence. pwrgd is immediately forced low when shdn goes low. pwrgd is blanked high impedance while any of the internal smps dacs are slewing during a vid transition, plus an additional 20s after the dac transition is com- pleted. for downward vid transitions, the upper threshold of the particular power-good fault comparators remains blanked until the output reaches regulation again. pwrgd is blanked high impedance for each smps whose internal dac is in off mode, and is pulled low if all three smps dacs are in off mode. pgd_in after the smps outputs reach the boot voltage, the MAX17480 switches to the serial-interface mode when pgd_in goes high. anytime during normal operation, a high-to-low transition on pgd_in causes the MAX17480 to slew all three internal dacs back to the stored boot vids. the svc and svd inputs are disabled during the time that pgd_in is low. the serial interface is reen- abled when pgd_in goes high again. figure 9 shows pgd_in timing.
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 35 shutdown when shdn goes low, the MAX17480 enters shutdown mode. pwrgd is pulled low immediately and forces all dh and dl low, and all three outputs are discharged through the 20 ? internal discharge fets through the csn pin for core smpss and through the out3 pin for nb smpss. vrhot temperature comparator the MAX17480 features an independent comparator with an accurate threshold (v hot ) that tracks the analog sup- ply voltage (v hot = 0.3v cc ). use a resistor- and thermis- tor-divider between v cc and gnd to generate a voltage-smps overtemperature monitor. place the thermis- tor as close as possible to the mosfets and inductors. place three individual thermistors near to each smps to monitor the temperature of the respective smps. when core smpss are in combined-mode operation, the cur- rent-balance circuit balances the currents between core smps phases. as such, the power loss and heat in each phase should be identical, apart from the effects of placement and airflow over each phase. single thermistors can be placed near either of the phases and still be effective for core smps temperature monitoring, and one thermistor can be saved. see figure 10. MAX17480 v cc thrm r thrm r ntc gnd place r ntc next to the hottest power component. MAX17480 v cc thrm r ptc2 r thrm gnd place r ptc1 , r ptc2 , and r ptc3 next to the respective smps's power component. r ptc1 r ptc3 figure 10. thrm configuration 20 s 20 s 2-bit boot vid, svc/svd inputs disabled psi_l pgd_in pwrgd smps v out (high dac target) (low dac target) smps v out svc/svd bus idle bus idle pulse-skipping mode target v out blank high-z blank high-z figure 9. pgd_in timing
MAX17480 amd 2-/3-output mobile serial vid controller 36 ______________________________________________________________________________________ fault protection (latched) output overvoltage protection (ovp) the overvoltage protection (ovp) circuit is designed to protect the cpu against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the MAX17480 continuously monitors the output for an overvoltage fault. the controller detects an ovp fault if the output voltage exceeds the set vid dac voltage by more than 300mv. the ovp threshold tracks the vid dac voltage except during a downward vid transition. during a downward vid transition, the ovp threshold is set at 1.85v (typ) until the output reaches regulation, when the ovp threshold is reset back to 300mv above the vid setting. when the ovp circuit detects an overvoltage fault in core smpss, it immediately sets the fault latch and forces the external low-side driver high on the faulted smps. the nonfaulted smpss are also shut down by turning on the internal passive discharge mosfet. the synchronous-rectifier mosfets of the faulted side are turned on with 100% duty, which rapidly discharges the output filter capacitor and forces the output low. if the condition that caused the overvoltage (such as a short- ed high-side mosfet) persists, the battery fuse blows. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. when the core smpss are configured in combined mode, the synchronous-rectifier mosfets of both phases are turned on with 100% duty in response to an overvoltage fault. passive shutdown is initiated for the nb smps. the nb smps has no ovp. output undervoltage protection (uvp) if any of the MAX17480 output voltages are 400mv below the target voltage, the controller sets the fault latch, shuts down all the smpss, and activates the internal passive discharge mosfet. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. v cc undervoltage-lockout (uvlo) protection if the v cc voltage drops below 4.2v (typ), the controller assumes that there is not enough supply voltage to make valid decisions and sets a fault latch. during a uvlo fault, the controller shuts down all the smpss immediately, forces dl and dh low, and pulls csn1, csn2, and out3 low through internal 20 ? discharge fets. if the v cc falls below the por threshold (1.8v, typ), dl is forced low even if it was previously high due to a latched overvoltage fault. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. v ddio undervoltage-lockout (uvlo) protection if the v ddio voltage drops below 0.7v (typ), the con- troller assumes that there is not enough supply voltage to make valid decisions and sets a uv fault latch. during v ddio uvlo, as with uvp, the controller shuts down all the smpss immediately, forces dl and dh low, and pulls csn1, csn2, and out3 low through internal 20 ? discharge fets. if the v cc falls below the por threshold (1.8v, typ), dl is forced low even if it was previously high due to a latched overvoltage fault. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. thermal fault protection the MAX17480 features a thermal fault protection circuit. when the junction temperature rises above +160 c, a thermal sensor sets the fault latch and shuts down immediately, forcing dh and dl low and turning on the 20 ? discharge fets for all smpss. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller after the junction temperature cools by 15 c. other fault protection (nonlatched) v in3 undervoltage-lockout (uvlo) protection if the v in3 voltage drops below 2.5v (typ), the controller assumes that there is not enough input voltage for nb smpss. if v in3 uvlo happens before or just after soft- start, the nb smps is disabled and the internal target voltage stays off. when the v in3 subsequently rises past its uvlo rising threshold 2.6v (typ), nb goes through the soft-start sequence with a 1mv/s slew rate. if v in3 uvlo happens while the MAX17480 is running, the nb smps is stopped, the nb target is reset to 0 immediately, and pwrgd is forced low. when v in3 subsequently rises above the uvlo rising threshold 2.6v (typ), the nb smps restarts with 1mv/s slew rate to the previous dac target. core smps mosfet gate drivers the dh and dl drivers are optimized for driving moder- ate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications where a large v in - v out differential exists. the high-side gate drivers (dh) source and sink 2.2a, and the low-side gate drivers (dl) source 2.7a and sink 8a. this ensures robust gate drive for high-current applications. the dh floating high-side mosfet drivers are powered by internal boost switch charge pumps at bst, while the dl syn- chronous-rectifier drivers are powered directly by the 5v bias supply (v dd ).
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 37 adaptive dead-time circuits monitor the dl and dh dri- vers and prevent either fet from turning on until the other is fully off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. there must be a low-resistance, low-inductance path from the dl and dh drivers to the mosfet gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17480 inter- prets the mosfet gates as off while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the internal pulldown transistor that drives dl low is robust, with a 0.25 ? (typ) on-resistance. this helps pre- vent dl from being pulled up due to capacitive coupling from the drain to the gate of the low-side mosfets when the inductor node (lx) quickly switches from ground to v in . applications with high input voltages and long inductive driver traces could require rising lx edges that do not pull up the low-side mosfets gate, causing shoot-through currents. the capacitive coupling between lx and dl created by the mosfets gate-to- drain capacitance (c rss ), gate-to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following minimum threshold: typically, adding a 4700pf capacitor between dl and power ground (c nl in figure 11), close to the low-side mosfets, greatly reduces coupling. do not exceed 22nf of total gate capacitance to prevent excessive turn-off delays. alternatively, shoot-through currents can be caused by a combination of fast high-side mosfets and slow low- side mosfets. if the turn-off delay time of the low-side mosfet is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 ? in series with bst slows down the high-side mosfet turn-on time, elimi- nating the shoot-through currents without degrading the turn-off time (r bst in figure 11). slowing down the high-side mosfet also reduces the lx node rise time, thereby reducing emi and high-frequency coupling responsible for switching noise. offset and address change for core smpss (option) the +12.5mv offset and the address change features of the MAX17480 can be selectively enabled and dis- abled by the option pin setting. when the offset is enabled, setting the psi_l bit to 0 disables the offset, reducing power consumption in the low-power state. see the core smps offset section for a detailed description of this feature. in addition, the address of the core smpss can be exchanged, allowing for flexible layout of the MAX17480 with respect to the cpu placement on the same or opposite sides of the pcb. table 5 shows the option pin voltage levels and the features that are enabled. vv c c gs th in rss iss () > ? ? ? ? ? ? MAX17480 n h n l (r bst )* (r bst )* optional?he resistor lowers emi by decreasing the switching node rise time. (c nl )* optional?he capacitor reduces lx-to-dl capacitive bst input (v in ) l dh lx v dd dl pgnd c bst (c nl )* c byp coupling that can cause shoot-through currents. figure 11. gate-drive circuit option offset enables smps1 address smps2 address v cc 0 bit 1 (vdd0) bit 2 (vdd1) 3.3v 0 bit 2 (vdd1) bit 1 (vdd0) 2v 1 bit 1 (vdd0) bit 2 (vdd1) gnd 1 bit 2 (vdd1) bit 1 (vdd0) table 5. option pin settings note: vdd0 refers to core0 and vdd1 refers to core1 for the amd cpu.
MAX17480 amd 2-/3-output mobile serial vid controller 38 ______________________________________________________________________________________ offset and current-limit setting for nb smps (ilim3) the offset and current-limit settings of the nb smps can be set by the ilim3 pin setting. table 6 shows the ilim3 pin voltage levels and the corresponding settings for the offset and current limit of the nb smps. the nb offset is always present regardless of psi_l setting. the i lx3min minimum current-limit threshold in skip mode is precisely 25% of the corresponding positive current-limit threshold. smps design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil- tering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load cur- rent (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing components. modern notebook cpus generally exhibit i load = i load(max) x 80%. for multiphase systems, each phase supports a frac- tion of the load, depending on the current balancing. when properly balanced, the load current is evenly distributed among each phase: where ph is the total number of active phases. core switching frequency: this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the optimum frequency is also a moving target, due to rapid improvements in mosfet technology that are making higher frequencies more practical. when selecting a switching frequency, the minimum on-time at the highest input voltage and lowest output voltage must be greater than the 150ns (max) mini- mum on-time specification in the electrical characteristics table: v out(min) /v in(max) x t sw > t on(min) a good rule is to choose a minimum on-time of at least 200ns. when in pulse-skipping operation (psi_l = 0), the minimum on-time must take into consideration the time needed for proper skip-mode operation. the on- time for a skip pulse must be greater than the 170ns (max) minimum on-time specification in the electrical characteristics table: inductor operating point: this choice provides trade-offs between size vs. efficiency and transient response vs. output noise. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher out- put noise due to increased ripple current. the mini- mum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. t lv rv v on min idle sense in max out min () () () ? () i i load phase load ph () = ilim3 peak current limit (a) skip current limit (a) max dc current (a) full-load droop (mv) offset (mv) v cc 5.25 1.3 4.75 -26.13 12.5 gnd 4.25 1.05 3.75 -20.63 12.5 table 6. ilim3 setting
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 39 core smps design procedure core inductor selection by design, the amd mobile serial vid application should regard each of the MAX17480 smpss as inde- pendent, single-phase smpss. the switching frequen- cy and operating point (% ripple current or lir) determine the inductor value as follows: where i load(max) is the maximum current per phase, and f sw is the switching frequency per phase. find a low-loss inductor with the lowest possible dc resistance that fits in the allotted dimensions. if using a swinging inductor (where the inductance decreases lin- early with increasing current), evaluate the lir with properly scaled inductance values. for the selected inductance value, the actual peak-to-peak inductor ripple current ( ? i inductor ) is defined by: ferrite cores are often the best choice, although pow- dered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): core peak inductor current limit (ilim12) the MAX17480 overcurrent protection employs a peak current-sensing algorithm that uses either current- sense resistors or the inductors dcr as the current- sense element (see the current sense section). since the controller limits the peak inductor current, the maxi- mum average load current is less than the peak cur- rent-limit threshold by an amount equal to half the inductor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and input-to-out- put voltage difference. when combined with the output undervoltage-protection circuit, the system is effectively protected against excessive overload conditions. the peak current-limit threshold is set by the voltage difference between ilim and ref using an external resistor-divider: v cs(pk) = v csp _ - v csn _ = 0.052 x (v ref - v ilim12 ) i limit(pk) = v cs(pk) /r sense where r sense is the resistance value of the current- sense element (inductors dcr or current-sense resis- tor), and i limit(pk) is the desired peak current limit (per phase). the peak current-limit threshold voltage adjust- ment range is from 10mv to 50mv. core output capacitor selection the output filter capacitor must have low enough esr to meet output ripple and load-transient requirements. in cpu v core converters and other applications where the output is subject to large load transients, the output capacitors size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitors size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tors esr. when operating multiphase systems out-of- phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage (v ripple ) by reducing the total inductor ripple current. for nonoverlapping, multiphase operation (v in v out ), the maximum esr to meet the output-ripple-voltage requirement is: where f sw is the switching frequency per phase. the actual capacitance value required relates to the physi- cal size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capac- itor selection is usually limited by esr and voltage rat- ing rather than by capacitance value (this is true of polymer types). the capacitance value required is determined primarily by the output transient-response requirements. low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the out- put filter capacitors by a sudden load step. therefore, the amount of output soar when the load is removed is a function of the output voltage and inductor value. the minimum output capacitance required to prevent over- shoot (v soar ) due to stored inductor energy can be calculated as: c il vv out load max out soar () ? () 2 2 r vf l vv v v esr in sw in out out ripple ? () ? ? ? ? ? ? ? ? rr v i esr pcb step load max + () ? () i i i peak load max ph inductor = ? ? ? ? ? ? + ? ? ? ? ? ? () ? 2 ? i vvv vf l inductor out in out in sw = ? () l vv fi lir v v in out sw load max out in = ? ? ? ? ? ? ? ? ? ? ? () ? ? ? ? ?
MAX17480 amd 2-/3-output mobile serial vid controller 40 ______________________________________________________________________________________ when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. core input capacitor selection the input capacitor must meet the ripple-current requirement (i rms ) imposed by the switching currents. for a dual 180 interleaved controller, the out-of-phase operation reduces the rms input ripple current, effec- tively lowering the input capacitance requirements. when both outputs operate with a duty cycle less than 50% (v in > 2v out ), the rms input ripple current is defined by the following equation: where i in is the average input current: in combined mode (gnds1 = v ddio or gnds2 = v ddio ) with both phases active, the input rms current simplifies to: for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. if the MAX17480 is operated as the second stage of a two-stage power-conversion sys- tem, tantalum input capacitors are acceptable. in either configuration, choose an input capacitor that exhibits less than +10 c temperature rise at the rms input cur- rent for optimal circuit longevity. core voltage positioning and loop compensation voltage positioning dynamically lowers the output volt- age in response to the load current, reducing the output capacitance and processors power-dissipation require- ments. the controller uses a transconductance amplifier to set the transient ac and dc output-voltage droop (figure 5). the fbac and fbdc configuration adjusts the steady-state regulation voltage as a function of the load. this adjustability allows flexibility in the selected current-sense resistor value or inductor dcr, and allows smaller current-sense resistance to be used, reducing the overall power dissipated. core transient droop and stability the inductor current ripple sensed across the current- sense inputs (csp_ - csn_) generates a proportionate current out of the fbac pin. this ac current flowing across the effective impedance at fbac generates an ac ripple voltage. actual stability, however, depends on the ac voltage at the fbdc pin, and not on the fbac pin. based on the configuration shown in figure 5, the ripple voltage at the fbdc pin can only be less than, or equal to, the ripple at the fbac pin. with the requirement that r fbdc = r fbac , and (z cfb //r fb ) < 10% of r fbac , then: where g m (fbac_) is typically 2ms as defined in the electrical characteristics table, r sense_ is the effective value of the current-sense element that is used to pro- vide the (csp_, csn_) current-sense voltage, and f sw is the selected switching frequency. based on the above requirement for r fbac and r fbdc , and with the other requirement for r fbdc defined in the core steady-state voltage positioning (dc droop) sec- tion, r fbac and r fbdc can be chosen. the resultant ac droop is: capacitor c fb is required when the r droop_dc is less than r droop_ac . choose c fb according to the following equation: core steady-state voltage positioning with r droop_ac defined, the steady-state voltage- positioning slope, r droop_dc , can only be less than, or at most equal to, r droop_ac : choose the r fbdc and r fbac already previously cho- sen, then select r fb to give the desired droop. dc droop is typically used together with the +12.5mv offset feature to keep within the dc tolerance window of the application. see the offset and address change for core smpss (option) section. r rrr rrr g droop dc fbdc fbac sense fbac fbdc fb m _ = ++ ( () fbac crr r t fb fb fbac fbdc sw + ? ? ? ? = //( ) 3 r rrr rr g droop ac fbdc fbac sense fbac fbdc mfba _( + c c) rr cfr g fbac fbdc out sw sense m fbac = 1 _( ) ii v v v v rms out out in out in = ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2 i v v i v v i in out in out out in out = ? ? ? ? ? ? + ? ? ? ? ? ? 1 1 2 2 i v v ii i v v rms out in out out in out i = ? ? ? ? ? ? ? () + 1 11 2 n n out out in ii i ? ? ? ? ? ? ? () 22
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 41 core power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high-load-current capability when using high-voltage (> 20v) ac adapters. low- current applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but with higher c gate ). conversely, if the loss- es at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h (increasing r ds(on) to lower c gate ). if v in does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. choose a low-side mosfet that has the lowest possible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two 8-pin sos, dpak, or d2pak), and is reasonably priced. make sure that the dl gate dri- ver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to- drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems might occur (see the core smps mosfet gate drivers section). core mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at the minimum input voltage: where i load is the per-phase current. generally, a small high-side mosfet is desired to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissipation often limits how small the mosfet can be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses do not usually become an issue until the input is greater than approximately 15v. calculating the power dissipation in the high-side mosfet (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : : where c rss is the reverse transfer capacitance of n h , i gate is the peak gate-drive source/sink current (1a, typ), and i load is the per-phase current. switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied, due to the squared term in the c x v in 2 x f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased from v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) , but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro- tect against this possibility, the circuit can be overde- signed to tolerate: where i peak(max) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a good-sized heatsink to handle the over- load power dissipation. choose a schottky diode (d l ) with a forward voltage low enough to prevent the low-side mosfet body diode from turning on during the dead time. as a gen- eral rule, select a diode with a dc current rating equal to 1/3 the load current per phase. this diode is optional and can be removed if efficiency is not critical. core boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements of the high-side mosfets. typically, 0.1f ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1f. for these applications, ii i i load max peak max inductor peak max () () ( =? = ? 2 ) ) () ? ? ? ? ? ? ? ? ? ilir load max 2 pd (n resistive) = l 1 ? ? ? ? ? ? ? ? ? ? ? ? v v out in max () ? ? ? ? ? ? ? ? ? ? ? ? i r load total ds on 2 () pd (n switching) = h v cf i in max rss sw gat () () 2 e e load i ? ? ? ? ? ? pd (n resistive) = h v v ir out in load ds o ? ? ? ? ? ? 2 (n n)
MAX17480 amd 2-/3-output mobile serial vid controller 42 ______________________________________________________________________________________ select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets gates: where n is the number of high-side mosfets used for one smps, and q gate is the gate charge specified in the mosfets data sheet. for example, assume two irf7811w n-channel mosfets are used on the high side. according to the manufacturers data sheet, a single irf7811w has a maximum gate charge of 24nc (v gs = 5v). using the above equation, the required boost capacitance would be: : selecting the closest standard value, this example requires a 0.22f ceramic capacitor. nb smps design procedure nb inductor selection the switching frequency and operating point (% ripple current or lir) determine the inductor value as follows: : where i load3(max) is the maximum current and f sw3 is the switching frequency of the nb regulator. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. if using a swinging inductor (where the inductance decreases linearly with increasing current), evaluate the lir with properly scaled inductance values. for the selected inductance value, the actual peak-to-peak inductor rip- ple current ( ? i inductor ) is defined by: : ferrite cores are often the best choice, although pow- dered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak3 ): nb peak inductor current limit (ilim3) the MAX17480 nb regulator overcurrent protection employs a peak current-sensing algorithm that uses the high-side mosfet r on(nh3) as the current-sense ele- ment. since the controller limits the peak inductor cur- rent, the maximum average load current is less than the peak current-limit threshold by an amount equal to half the inductor ripple current. therefore, the maximum load capability is a function of the current-limit setting, inductor value, switching frequency, and input-to-out- put voltage difference. when combined with the output undervoltage-protection circuit, the system is effectively protected against excessive overload conditions. the peak current-limit threshold is set by the ilim3 pin setting (see the offset and current-limit setting for nb smps (ilim3) section). nb output capacitor selection the output filter capacitor must have low enough esr to meet output ripple and load-transient requirements. in cpu v core converters and other applications where the output is subject to large load transients, the output capacitors size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: : the output capacitors size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitors esr. for single-phase operation, the maximum esr to meet the output-ripple-voltage requirement is: : where f sw3 is the switching frequency. the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, capacitor selection is usually limited by esr and voltage rating rather than by capacitance value (this is true of polymer types). r vf l vv v v esr in sw in out out ri ? () ? ? ? ? ? ? ? ? 333 333 p pple3 rr v i esr pcb step load max + () ? () ii i peak load max inductor 33 2 =+ ? ? ? ? ? ? () ? ? i vvv vf l inductor out in out in sw = ? () 33 3 333 l vv fi lir v in out sw load max out 3 33 33 = ? ? ? ? ? ? ? ? ? () 3 3 3 v in ? ? ? ? ? ? c nc mv f bst = = . 224 200 024 c nq mv bst gate = 200
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 43 the capacitance value required is determined primarily by the stability requirements. however, the soar and sag calculations are still provided here for reference. low inductor values allow the inductor current to slew faster, replenishing charge removed from or added to the output filter capacitors by a sudden load step. therefore, the amount of output soar and sag when the load is applied or removed is a function of the output voltage and inductor value. the soar and sag voltages are calculated as: : where d max is the maximum duty cycle of the nb smps as listed in the electrical characteristics table, t sw3 is the nb switching period programmed by the osc pin, and ? t equals v out /v in x t sw when in forced- pwm mode, or l x i lx3min /(v in - v out ) when in pulse- skipping mode. when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. nb input capacitor selection the input capacitor must meet the ripple-current require- ment (i rms ) imposed by the switching currents. the i rms requirements can be determined by the following equation: : the worst-case rms current requirement occurs when operating with v in3 = 2v out3 . at this point, the above equation simplifies to i rms = 0.5 x i load3 . for most applications, nontantalum chemistries (ceramic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents typical of sys- tems with a mechanical switch or connector in series with the input. the MAX17480 nb regulator is operated as the second stage of a two-stage power-conversion system. tantalum input capacitors are acceptable. choose an input capacitor that exhibits less than 10 c temperature rise at the rms input current for optimal circuit longevity. nb steady-state voltage positioning voltage positioning dynamically lowers the output volt- age in response to the load current, reducing the out- put capacitance and processors power-dissipation requirements. for nb, the load line is generated by sensing the inductor current through the high-side mosfet on-resistance (r on(nh3) ), and is internally preset to -5.5mv/a (typ). this guarantees the output voltage to stay in the static regulation window over the maximum load conditions per amd specifications. see table 6 for full-load voltage droop according to differ- ent ilim3 settings. nb transient droop and stability the voltage-positioned load-line of the nb smps also provides the ac ripple voltage required for stability. to maintain stability, the output capacitive ripple must be kept smaller than the internal ac ripple voltage. hence, a minimum nb output capacitance is required as calcu- lated below: : where r droop3(min) is 4mv/a as defined in the electrical characteristics table, and f sw3 is the nb switching frequency programmed by the osc pin. svi applications information i 2 c bus-compatible interface the MAX17480 is a receive-only device. the 2-wire seri- al bus (pins svc and svd) is designed to attach on a low-voltage i 2 c-like bus. in the amd mobile application, the cpu directly drives the bus at a speed of 3.4mhz. the cpu has a push-pull output driving to the v ddio voltage level. external pullup resistors are not required. when not used in the specific amd application, the ser- ial interface can be driven to as high as 2.5v, and can operate at the lower speeds (100khz, 400khz, or 1.7mhz). at lower clock speeds, external pullup resis- tors can be used for open-drain outputs. connect both svc and svd lines to v ddio through individual pullup resistors. calculate the required value of the pullup resistors using: : where t r is the rise time, and should be less than 10% of the clock period. c bus is the total capacitance on the bus. the MAX17480 is compatible with the standard svi inter- face protocol as defined in the following subsections. figure 12 shows the svi bus start, stop, and data change conditions. r t pullup r c bus c fr v v out sw droop min out in 3 33 3 3 1 2 1 > + ? ? ? ? ? ? () i i v vvv rms load in out in out = ? ? ? ? ? ? ? () 3 3 33 3 v il vc v i soar load max out out sag 3 3 2 3 33 3 2 = () = ? ? () l load max out in max out l cvdv i 3 2 3 33 3 2 () () ? () + ? l load max sw out tt c 33 3 () ? () ?
MAX17480 amd 2-/3-output mobile serial vid controller 44 ______________________________________________________________________________________ bus not busy the svi bus is not busy when both data and clock lines remain high. data transfers can be initiated only when the bus is not busy. figure 13 shows the svi bus acknowledge. start data transfer (s) starting from an idle bus state (both svc and svd are high), a high-to-low transition of the data (svd) line while the clock (svc) is high determines a start condition. all commands must be preceded by a start condition. stop data transfer (p) a low-to-high transition of the sda line while the clock (svc) is high determines a stop condition. all opera- tions must be ended with a stop condition. slave address after generating a start condition, the bus master transmits the slave address consisting of a 7-bit device code (110xxxx) for the MAX17480. since the MAX17480 is a write-only device, the eighth bit of the slave address is 0. the MAX17480 monitors the bus for its corresponding slave address continuously. it gener- ates an acknowledge bit if the slave address was true and it is not in a programming mode. svd data valid the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. the device that acknowledges has to pull down the svd line during the acknowledge clock pulse so that the svd line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. see figure 13. data output by master data output by MAX17480 svc from master s start condition d7 1 clk1 2 clk2 8 clk8 9 clk9 d6 d0 not acknowledge acknowledge acknowledge clock pulse figure 13. svi bus acknowledge svd svc s start condition stop condition data line stable data valid change of data allowed p figure 12. svi bus start, stop, and data change conditions
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 45 command byte a complete command consists of a start condition (s) followed by the MAX17480s slave address and a data phase, followed by a stop condition (p). for the slave address, bits 6:4 are always 110 and bit 3 is x (dont care). the wr bit should always be 1 since read functions are not supported. figure 14 is the svi bus data-transfer summary. table 7 is a description of the svi send byte address and table 8 describes serial vid 8-bit field encoding. smps applications information duty-cycle limits minimum input voltage the minimum input operating voltage (dropout voltage) is restricted by stability requirements, not the minimum off-time (t off(min) ). the MAX17480 does not include slope compensation, so the controller becomes unsta- ble with duty cycles greater than 50% per phase: v in(min) 2v out(max) however, the controller can briefly operate with duty cycles over 50% during heavy load transients. table 7. svi send byte address description table 8. serial vid 8-bit field encoding bit description 6:4 always 110b. 3 xdont care. 2 vdd1, if set then the following data byte contains the vid for vdd1. bit 2 is ignored in combined mode (gnds1 or gnds2 = v ddio ). vdd1 refers to core1 of the amd cpu. 1 vdd0, if set then the following data byte contains the vid for vdd0 in separate mode, and the unified vdd in combined mode. vdd0 refers to core0 of the amd cpu. 0 vddnb, if set then the following data byte contains the vid for vddnb. bit description 7 psi_l: power-save indicator 0 means the processor is at an optimal load and the smps(s) can enter power-saving mode. the smps operates in pulse-skipping mode after exiting the boot mode. offset is disabled if previously enabled by the option pin. the MAX17480 enters 1-phase operation if in combined mode (gnds1 or gnds2 = h). 1 means the processor is in a high current- consumption state. the smps operates in forced- pwm mode after exiting the boot mode. offset is enabled if previously enabled by the option pin. the MAX17480 returns to 2-phase operation if in combined mode (gnds1 or gnds2 = h). 6:0 svid[6:0] as defined in table 7. figure 14. svi bus data transfer summary set dac and psi_l slave address s p stop start psi_l bit6 1 1 0 x nb wr (write) = 0 ack vdd1 (core1) vdd0 (core0) fixed values bit0 bit5 bit4 bit3 bit2 bit1 ack
MAX17480 amd 2-/3-output mobile serial vid controller 46 ______________________________________________________________________________________ maximum input voltage the MAX17480 controller has a minimum on-time, which determines the maximum input operating voltage that maintains the selected switching frequency. with higher input voltages, each pulse delivers more energy than the output is sourcing to the load. at the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, resulting in pulse-skipping operation regardless of the operating mode selected by psi_l. this allows the controller to maintain regulation above the maximum input voltage, but forces the con- troller to effectively operate with a lower switching fre- quency. this results in an input threshold voltage at which the controller begins to skip pulses (v in(skip) ): : where f sw is the per-phase switching frequency set by the osc resistor, and t on(min) is 150ns (max) minus the drivers turn-on delay (dl low to dh high). for the best high-voltage performance, use the slowest switching frequency setting (100khz per phase, r osc = 432k ? ). pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 15). if possible, mount all the power components on the top side of the board with their ground terminals flush against one another, and mount the controller and ana- log components on the bottom layer so the internal ground layers shield the analog components from any noise generated by the power components. follow these guidelines for good pcb layout: ? keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. ? connect all analog grounds to a separate solid cop- per plane; then connect the analog ground to the gnd pins of the controller. the following sensitive components connect to analog ground: v cc and v ddio bypass capacitors, remote sense and gnds bypass capacitors, and the resistive connections (ilim12, osc, time). ? keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pcb (2oz vs. 1oz) can enhance full-load effi- ciency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance causes a measurable effi- ciency penalty. ? connections for current limiting (csp, csn) and volt- age positioning (fbs, gnds) must be made using kelvin-sense connections to guarantee the current- sense accuracy. place current-sense filter capacitors and voltage-positioning filter capacitors as close as possible to the ic. ? route high-speed switching nodes and driver traces away from sensitive analog areas (ref, v cc , fbac, fbdc, out3, etc.). make all pin-strap control input connections ( shdn , pgd_in, option) to analog ground or v cc rather than power ground or v dd . ? route the high-speed serial-interface signals (svc, svd) in parallel, keeping the trace lengths identical. keep the svc and svd away from the high-current switching paths. ? keep the drivers close to the mosfet, with the gate- drive traces (dl, dh, lx, and bst) short and wide to minimize trace resistance and inductance. this is essential for high-power mosfets that require low- impedance gate drivers to avoid shoot-through cur- rents. ? when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet rather than to allow distance between the inductor and the low- side mosfet or between the inductor and the output filter capacitor. layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and dl anode). if possible, make all these connections on the top layer with wide, copper- filled areas. for the nb smps, place cin3 and l3 as near as possible to the MAX17480, using multi- ple vias to reduce inductance when connecting the different layers. 2) use multiple vias to connect the exposed backside to the power ground plane (pgnd) to allow for a low- impedance path for the smps3 internal low-side mosfet. 3) mount the MAX17480 close to the low-side mosfets. the dl gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the driver ic). 4) group the gate-drive components (bst capacitors, v dd bypass capacitor) together near the MAX17480. vv ft in skip out sw on min () () = ? ? ? ? ? ? ? ? 1
MAX17480 amd 2-/3-output mobile serial vid controller ______________________________________________________________________________________ 47 5) make the dc-dc controller ground connections as shown in the standard application circuit (figure 2). this diagram can be viewed as having three sepa- rate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the pgnd, v dd bypass capacitor, and driver ic ground connection go; and the con- trollers analog ground plane, where sensitive ana- log components, the MAX17480s agnd pin, and v cc bypass capacitor go. the controllers analog ground plane (agnd) must meet the power ground plane (pgnd) only at a single point directly beneath the ic. the power ground plane should connect to the high-power output ground with a short, thick metal trace from pgnd to the source of the low-side mosfets (the middle of the star ground). 6) connect the output power planes (v core , v out3 , and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the cpu as is practical. v ddnb v core1 v core0 c out c out inductor power ground inductor c out c out split core cpu socket c in c in c in c in agnd pin connect the exposed pad to power gnd using multiple vias + c vcc c vdd c in3 l3 c out3 c eq r ntc r2 r1 csp csn csp csn kelvin-sense vias to inductor pad kelvin-sense vias under the inductor (refer to evaluation kit) inductor dcr sensing figure 15. pcb layout example
MAX17480 amd 2-/3-output mobile serial vid controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 48 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. pin configuration MAX17480 pgnd thin qfn (5mm 5mm) top view 35 36 34 33 12 11 13 ilim3 in3 lx3 lx3 bst3 14 ilim12 bst1 v dd dl2 lx1 dh1 vrhot bst2 lx2 12 csn1 4567 27 28 29 30 26 24 23 22 fbdc1 fbac1 csp2 csn2 fbdc2 fbac2 in3 dl1 3 25 37 gnds1 gnds2 38 39 40 option osc time v ddio svc svd csp1 32 15 pgd_in v cc 31 16 17 18 19 20 pwrgd shdn out3 agnd dh2 89 *ep *exposed pad. 10 21 thrm + chip information transistor count: 24,311 process: bicmos package type package code document no. 40 tqfn-ep t4055-2 21-0140 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .

▲Up To Search▲

Price & Availability of MAX17480

	To Download MAX17480 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .